Matching Items (11)
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- All Subjects: energy
- Creators: Goryll, Michael
- Member of: ASU Electronic Theses and Dissertations
- Status: Published
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for implementing high-throughput DSP systems that are also energy-efficient. Data-path components such as adders and multipliers are evaluated with respect to critical path delay, energy and Energy-Delay Product (EDP). A new design for a RBR adder with very good EDP performance has been proposed. The corresponding RBR parallel adder has a much lower critical path delay and EDP compared to two's complement carry select and carry look-ahead adder implementations. Next, several RBR multiplier architectures are investigated and their performance compared to two's complement systems. These include two new multiplier architectures: a purely RBR multiplier where both the operands are in RBR form, and a hybrid multiplier where the multiplicand is in RBR form and the other operand is represented in conventional two's complement form. Both the RBR and hybrid designs are demonstrated to have better EDP performance compared to conventional two's complement multipliers. The hybrid multiplier is also shown to have a superior EDP performance compared to the RBR multiplier, with much lower implementation area. Analysis on the effect of bit-precision is also performed, and it is shown that the performance gain of RBR systems improves for higher bit precision. Next, in order to demonstrate the efficacy of the RBR representation at the system-level, the performance of RBR and hybrid implementations of some common DSP kernels such as Discrete Cosine Transform, edge detection using Sobel operator, complex multiplication, Lifting-based Discrete Wavelet Transform (9, 7) filter, and FIR filter, is compared with two's complement systems. It is shown that for relatively large computation modules, the RBR to two's complement conversion overhead gets amortized. In case of systems with high complexity, for iso-throughput, both the hybrid and RBR implementations are demonstrated to be superior with lower average energy consumption. For low complexity systems, the conversion overhead is significant, and overpowers the EDP performance gain obtained from the RBR computation operation.
ContributorsMahadevan, Rupa (Author) / Chakrabarti, Chaitali (Thesis advisor) / Kiaei, Sayfe (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Development of New Front Side Metallization Method of Aluminum Electroplating for Silicon Solar Cell
Description
In this thesis, the methods of aluminum electroplating in an ionic liquid for silicon solar cell front side metallization were studied. It focused on replacing the current silver screen printing with an alternative metallization technology using a low-cost Earth-abundant metal for mass production, due to the high cost and limited availability of silver. A conventional aluminum electroplating method was employed for silicon solar cells fabrication on both p-type and n-type substrates. The highest efficiency of 17.9% was achieved in the n-type solar cell with a rear junction, which is comparable to that of the same structure cell with screen printed silver electrodes from industrial production lines. It also showed better spiking resistant performance than the common structure p-type solar cell. Further efforts were put on the development of a novel light-induced plating of aluminum technique. The aluminum was deposited directly on a silicon substrate without the assistance of a conductive seed layer, thus simplified and reduced the process cost. The plated aluminum has good adhesion to the silicon surface with the resistivity as low as 4×10–6 -cm. A new demo tool was designed and set up for the light-induced plating experiment, aiming to utilize this technique in large-size solar cells fabrication and mass production. Besides the metallization methods, a comprehensive sensitivity analysis for the efficiency dispersion in the production of crystalline-Si solar cells was presented based on numerical simulations. Temperature variation in the diffusion furnace was the most significant cause of the efficiency dispersion. It was concluded that a narrow efficiency range of ±0.5% absolute is achievable if the emitter diffusion temperature is confined to a 13˚C window, while other cell parameters vary within their normal windows. Possible methods to minimize temperature variation in emitter diffusion were proposed.
ContributorsWang, Laidong (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2018
Description
ABSTRACT
Autonomous smart windows may be integrated with a stack of active components, such as electrochromic devices, to modulate the opacity/transparency by an applied voltage. Here, we describe the processing and performance of two classes of visibly-transparent photovoltaic materials, namely inorganic (ZnO thin film) and fully organic (PCDTBT:PC70BM), for integration with electrochromic stacks.
Sputtered ZnO (2% Mn) films on ITO, with transparency in the visible range, were used to fabricate metal-semiconductor (MS), metal-insulator-semiconductor (MIS), and p-i-n heterojunction devices, and their photovoltaic conversion under ultraviolet (UV) illumination was evaluated with and without oxygen plasma-treated surface electrodes (Au, Ag, Al, and Ti/Ag). The MS Schottky parameters were fitted against the generalized Bardeen model to obtain the density of interface states (Dit ≈ 8.0×1011 eV−1cm−2) and neutral level (Eo ≈ -5.2 eV). These devices exhibited photoconductive behavior at λ = 365 nm, and low-noise Ag-ZnO detectors exhibited responsivity (R) and photoconductive gain (G) of 1.93×10−4 A/W and 6.57×10−4, respectively. Confirmed via matched-pair analysis, post-metallization, oxygen plasma treatment of Ag and Ti/Ag electrodes resulted in increased Schottky barrier heights, which maximized with a 2 nm SiO2 electron blocking layer (EBL), coupled with the suppression of recombination at the metal/semiconductor interface and blocking of majority carriers. For interdigitated devices under monochromatic UV-C illumination, the open-circuit voltage (Voc) was 1.2 V and short circuit current density (Jsc), due to minority carrier tunneling, was 0.68 mA/cm2.
A fully organic bulk heterojunction photovoltaic device, composed of poly[N-9’-heptadecanyl-2,7-carbazole-alt-5,5-(4’,7’-di-2-thienyli2’,1’,3’-benzothiadiazole)]:phenyl-C71-butyric-acidmethyl (PCDTBT:PC70BM), with corresponding electron and hole transport layers, i.e., LiF with Al contact and conducting
on-conducting (nc) PEDOT:PSS (with ITO/PET or Ag nanowire/PDMS contacts; the illuminating side), respectively, was developed. The PCDTBT/PC70BM/PEDOT:PSS(nc)/ITO/PET stack exhibited the highest performance: power conversion efficiency (PCE) ≈ 3%, Voc = 0.9V, and Jsc ≈ 10-15 mA/cm2. These stacks exhibited high visible range transparency, and provided the requisite power for a switchable electrochromic stack having an inkjet-printed, optically-active layer of tungsten trioxide (WO3), peroxo-tungstic acid dihydrate, and titania (TiO2) nano-particle-based blend. The electrochromic stacks (i.e., PET/ITO/LiClO4/WO3 on ITO/PET and Ag nanowire/PDMS substrates) exhibited optical switching under external bias from the PV stack (or an electrical outlet), with 7 s coloration time, 8 s bleaching time, and 0.36-0.75 optical modulation at λ = 525 nm. The devices were paired using an Internet of Things controller that enabled wireless switching.
Autonomous smart windows may be integrated with a stack of active components, such as electrochromic devices, to modulate the opacity/transparency by an applied voltage. Here, we describe the processing and performance of two classes of visibly-transparent photovoltaic materials, namely inorganic (ZnO thin film) and fully organic (PCDTBT:PC70BM), for integration with electrochromic stacks.
Sputtered ZnO (2% Mn) films on ITO, with transparency in the visible range, were used to fabricate metal-semiconductor (MS), metal-insulator-semiconductor (MIS), and p-i-n heterojunction devices, and their photovoltaic conversion under ultraviolet (UV) illumination was evaluated with and without oxygen plasma-treated surface electrodes (Au, Ag, Al, and Ti/Ag). The MS Schottky parameters were fitted against the generalized Bardeen model to obtain the density of interface states (Dit ≈ 8.0×1011 eV−1cm−2) and neutral level (Eo ≈ -5.2 eV). These devices exhibited photoconductive behavior at λ = 365 nm, and low-noise Ag-ZnO detectors exhibited responsivity (R) and photoconductive gain (G) of 1.93×10−4 A/W and 6.57×10−4, respectively. Confirmed via matched-pair analysis, post-metallization, oxygen plasma treatment of Ag and Ti/Ag electrodes resulted in increased Schottky barrier heights, which maximized with a 2 nm SiO2 electron blocking layer (EBL), coupled with the suppression of recombination at the metal/semiconductor interface and blocking of majority carriers. For interdigitated devices under monochromatic UV-C illumination, the open-circuit voltage (Voc) was 1.2 V and short circuit current density (Jsc), due to minority carrier tunneling, was 0.68 mA/cm2.
A fully organic bulk heterojunction photovoltaic device, composed of poly[N-9’-heptadecanyl-2,7-carbazole-alt-5,5-(4’,7’-di-2-thienyli2’,1’,3’-benzothiadiazole)]:phenyl-C71-butyric-acidmethyl (PCDTBT:PC70BM), with corresponding electron and hole transport layers, i.e., LiF with Al contact and conducting
on-conducting (nc) PEDOT:PSS (with ITO/PET or Ag nanowire/PDMS contacts; the illuminating side), respectively, was developed. The PCDTBT/PC70BM/PEDOT:PSS(nc)/ITO/PET stack exhibited the highest performance: power conversion efficiency (PCE) ≈ 3%, Voc = 0.9V, and Jsc ≈ 10-15 mA/cm2. These stacks exhibited high visible range transparency, and provided the requisite power for a switchable electrochromic stack having an inkjet-printed, optically-active layer of tungsten trioxide (WO3), peroxo-tungstic acid dihydrate, and titania (TiO2) nano-particle-based blend. The electrochromic stacks (i.e., PET/ITO/LiClO4/WO3 on ITO/PET and Ag nanowire/PDMS substrates) exhibited optical switching under external bias from the PV stack (or an electrical outlet), with 7 s coloration time, 8 s bleaching time, and 0.36-0.75 optical modulation at λ = 525 nm. The devices were paired using an Internet of Things controller that enabled wireless switching.
ContributorsAzhar, Ebraheem (Author) / Yu, Hongbin (Thesis advisor) / Dey, Sandwip (Thesis advisor) / Goryll, Michael (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2018
Description
To date, the most popular and dominant material for commercial solar cells is
crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out
of all commercial solar cells. Although the potential of crystalline-Si solar cells in
supplying energy demands is enormous, their future growth will likely be constrained
by two major bottlenecks. The first is the high electricity input to produce
crystalline-Si solar cells and modules, and the second is the limited supply of silver
(Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching
terawatt-scale deployment, which means the electricity produced by crystalline-Si
solar cells would never fulfill a noticeable portion of our energy demands in the future.
In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al)
electroplating has been developed as an alternative metallization technique in the
fabrication of crystalline-Si solar cells. The plating is carried out in a
near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been
found that dense, adherent Al deposits with resistivity in the high 10^–6 ohm-cm range
can be reproducibly obtained directly on Si substrates and nickel seed layers. An
all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al
back electrode, has been successfully demonstrated based on commercial p-type
monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further
optimization of the cell fabrication process, in particular a suitable patterning
technique for the front silicon nitride layer, is expected to increase the efficiency of
the cell to ~18%. This shows the potential of Al electroplating in cell metallization is
promising and replacing Ag with Al as the front finger electrode is feasible.
crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out
of all commercial solar cells. Although the potential of crystalline-Si solar cells in
supplying energy demands is enormous, their future growth will likely be constrained
by two major bottlenecks. The first is the high electricity input to produce
crystalline-Si solar cells and modules, and the second is the limited supply of silver
(Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching
terawatt-scale deployment, which means the electricity produced by crystalline-Si
solar cells would never fulfill a noticeable portion of our energy demands in the future.
In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al)
electroplating has been developed as an alternative metallization technique in the
fabrication of crystalline-Si solar cells. The plating is carried out in a
near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been
found that dense, adherent Al deposits with resistivity in the high 10^–6 ohm-cm range
can be reproducibly obtained directly on Si substrates and nickel seed layers. An
all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al
back electrode, has been successfully demonstrated based on commercial p-type
monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further
optimization of the cell fabrication process, in particular a suitable patterning
technique for the front silicon nitride layer, is expected to increase the efficiency of
the cell to ~18%. This shows the potential of Al electroplating in cell metallization is
promising and replacing Ag with Al as the front finger electrode is feasible.
ContributorsSun, Wen-Cheng (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
Description
A Microbial fuel cell (MFC) is a bio-inspired carbon-neutral, renewable electrochemical converter to extract electricity from catabolic reaction of micro-organisms. It is a promising technology capable of directly converting the abundant biomass on the planet into electricity and potentially alleviate the emerging global warming and energy crisis. The current and power density of MFCs are low compared with conventional energy conversion techniques. Since its debut in 2002, many studies have been performed by adopting a variety of new configurations and structures to improve the power density. The reported maximum areal and volumetric power densities range from 19 mW/m2 to 1.57 W/m2 and from 6.3 W/m3 to 392 W/m3, respectively, which are still low compared with conventional energy conversion techniques. In this dissertation, the impact of scaling effect on the performance of MFCs are investigated, and it is found that by scaling down the characteristic length of MFCs, the surface area to volume ratio increases and the current and power density improves. As a result, a miniaturized MFC fabricated by Micro-Electro-Mechanical System(MEMS) technology with gold anode is presented in this dissertation, which demonstrate a high power density of 3300 W/m3. The performance of the MEMS MFC is further improved by adopting anodes with higher surface area to volume ratio, such as carbon nanotube (CNT) and graphene based anodes, and the maximum power density is further improved to a record high power density of 11220 W/m3. A novel supercapacitor by regulating the respiration of the bacteria is also presented, and a high power density of 531.2 A/m2 (1,060,000 A/m3) and 197.5 W/m2 (395,000 W/m3), respectively, are marked, which are one to two orders of magnitude higher than any previously reported microbial electrochemical techniques.
ContributorsRen, Hao (Author) / Chae, Junseok (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Phillips, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
Description
A photovoltaic (PV) module is a series and parallel connection of multiple PV cells; defects in any cell can cause module power to drop. Similarly, a photovoltaic system is a series and parallel connection of multiple modules, and any low-performing module in the PV system can decrease the system output power. Defects in a solar cell include, but not limited to, the presence of cracks, potential induced degradation (PID), delamination, corrosion, and solder bond degradation. State-of-the-art characterization techniques to identify the defective cells in a module and defective module in a string are i) Current-voltage (IV) curve tracing, ii) Electroluminescence (EL) imaging, and iii) Infrared (IR) imaging. Shortcomings of these techniques include i) unsafe connection and disconnection need to be made with high voltage electrical cables, and ii) labor and time intensive disconnection of the photovoltaic strings from the system.This work presents a non-contact characterization technique to address the above two shortcomings. This technique uses a non-contact electrostatic voltmeter (ESV) along with a probe sensor to measure the surface potential of individual solar cells in a commercial module and the modules in a string in both off-grid and grid-connected systems. Unlike the EL approach, the ESV setup directly measures the surface potential by sensing the electric field lines that are present on the surface of the solar cell.
The off-grid testing of ESV on individual cells and multicells in crystalline silicon (c-Si) modules and on individual cells in cadmium telluride (CdTe) modules and individual modules in a CdTe string showed less than 2% difference in open circuit voltage compared to the voltmeter values. In addition, surface potential mapping of the defective cracked cells in a multicell module using ESV identified the dark, grey, and bright areas of EL images precisely at the exact locations shown by the EL characterization.
The on-grid testing of ESV measured the individual module voltages at maximum power point (Vmpp) and quantitatively identified the exact PID-affected module in the entire system. In addition, the poor-performing non-PID modules of a grid-connected PV system were also identified using the ESV technique.
ContributorsRaza, Hamza Ahmad (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Hacke, Peter (Committee member) / Arizona State University (Publisher)
Created2023
Description
Interdigitated back contact (IBC) solar cells have achieved the highest single junction silicon wafer-based solar cell power conversion efficiencies reported to date. This thesis is about the fabrication of a high-efficiency silicon heterojunction IBC solar cell for potential use as the bottom cell for a 3-terminal lattice-matched dilute-nitride Ga (In)NP(As)/Si monolithic tandem solar cell. An effective fabrication process has been developed and the process challenges related to open circuit voltage (Voc), series resistance (Rs), and fill factor (FF) are experimentally analyzed. While wet etching, the sample lost the initial passivation, and by changing the etchant solution and passivation process, the voltage at maximum power recovered to an initial value of over 710 mV before metallization. The factors reducing the series resistance loss in IBC cells were also studied. One of these factors was the Indium Tin Oxide (ITO) sputtering parameters, which impact the conductivity of the ITO layer and transport across the a-Si:H/ITO interface. For the standard recipe, the chamber pressure was 3.5 mTorr with no oxygen partial pressure, and the thickness of the ITO layer in contact with the a-Si:H layers, was optimized to 150 nm. The patterning method for the metal contacts and final annealing also change the contact resistance of the base and emitter stack layers. The final annealing step is necessary to recover the sputtering damage; however, the higher the annealing time the higher the final IBC series resistance. The best efficiency achieved was 19.3% (Jsc = 37 mA/cm2, Voc = 691 mV, FF = 71.7%) on 200 µm thick 1-15 Ω-cm n-type CZ C-Si with a designated area of 4 cm2.
ContributorsMoeini Rizi, Mansoure (Author) / Goodnick, Stephen (Thesis advisor) / Honsberg, Christina (Committee member) / Goryll, Michael (Committee member) / Smith, David (Committee member) / Bowden, Stuart (Committee member) / Arizona State University (Publisher)
Created2022
Description
Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2019