Matching Items (19)
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- All Subjects: energy
- All Subjects: Integrated circuits
- Creators: Qin, Jiangchao
- Creators: Kiaei, Sayfe
- Member of: ASU Electronic Theses and Dissertations
- Status: Published
Description
Efficiency of components is an ever increasing area of importance to portable applications, where a finite battery means finite operating time. Higher efficiency devices need to be designed that don't compromise on the performance that the consumer has come to expect. Class D amplifiers deliver on the goal of increased efficiency, but at the cost of distortion. Class AB amplifiers have low efficiency, but high linearity. By modulating the supply voltage of a Class AB amplifier to make a Class H amplifier, the efficiency can increase while still maintaining the Class AB level of linearity. A 92dB Power Supply Rejection Ratio (PSRR) Class AB amplifier and a Class H amplifier were designed in a 0.24um process for portable audio applications. Using a multiphase buck converter increased the efficiency of the Class H amplifier while still maintaining a fast response time to respond to audio frequencies. The Class H amplifier had an efficiency above the Class AB amplifier by 5-7% from 5-30mW of output power without affecting the total harmonic distortion (THD) at the design specifications. The Class H amplifier design met all design specifications and showed performance comparable to the designed Class AB amplifier across 1kHz-20kHz and 0.01mW-30mW. The Class H design was able to output 30mW into 16Ohms without any increase in THD. This design shows that Class H amplifiers merit more research into their potential for increasing efficiency of audio amplifiers and that even simple designs can give significant increases in efficiency without compromising linearity.
ContributorsPeterson, Cory (Author) / Bakkaloglu, Bertan (Thesis advisor) / Barnaby, Hugh (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Isolated DC/DC converters are used to provide electrical isolation between two supply domain systems. A fully integrated isolated DC/DC converter having no board-level components and fabricated using standard integrated circuits (IC) process is highly desirable in order to increase the system reliability and reduce costs. The isolation between the low-voltage side and high-voltage side of the converter is realized by a transformer that transfers energy while blocking the DC loop. The resonant mode power oscillator is used to enable high efficiency power transfer. The on-chip transformer is expected to have high coil inductance, high quality factors and high coupling coefficient to reduce the loss in the oscillation. The performance of a transformer is highly dependent on the vertical structure, horizontal geometry and other indispensable structures that make it compatible with the IC process such as metal fills and patterned ground shield (PGS). With the help of three-dimensional (3-D) electro-magnetic (EM) simulation software, the 3-D transformer model is simulated and the simulation result is got with high accuracy.
In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.
In this thesis an on-chip transformer for a fully integrated DC/DC converter using standard IC process is developed. Different types of transformers are modeled and simulated in HFSS. The performances are compared to select the optimum design. The effects of the additional structures including PGS and metal fills are also simulated. The transformer is tested with a network analyzer and the testing results show a good consistency with the simulation results when taking the chip traces, printed circuit board (PCB) traces, bond wires and SMA connectors into account.
ContributorsZhao, Yao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for implementing high-throughput DSP systems that are also energy-efficient. Data-path components such as adders and multipliers are evaluated with respect to critical path delay, energy and Energy-Delay Product (EDP). A new design for a RBR adder with very good EDP performance has been proposed. The corresponding RBR parallel adder has a much lower critical path delay and EDP compared to two's complement carry select and carry look-ahead adder implementations. Next, several RBR multiplier architectures are investigated and their performance compared to two's complement systems. These include two new multiplier architectures: a purely RBR multiplier where both the operands are in RBR form, and a hybrid multiplier where the multiplicand is in RBR form and the other operand is represented in conventional two's complement form. Both the RBR and hybrid designs are demonstrated to have better EDP performance compared to conventional two's complement multipliers. The hybrid multiplier is also shown to have a superior EDP performance compared to the RBR multiplier, with much lower implementation area. Analysis on the effect of bit-precision is also performed, and it is shown that the performance gain of RBR systems improves for higher bit precision. Next, in order to demonstrate the efficacy of the RBR representation at the system-level, the performance of RBR and hybrid implementations of some common DSP kernels such as Discrete Cosine Transform, edge detection using Sobel operator, complex multiplication, Lifting-based Discrete Wavelet Transform (9, 7) filter, and FIR filter, is compared with two's complement systems. It is shown that for relatively large computation modules, the RBR to two's complement conversion overhead gets amortized. In case of systems with high complexity, for iso-throughput, both the hybrid and RBR implementations are demonstrated to be superior with lower average energy consumption. For low complexity systems, the conversion overhead is significant, and overpowers the EDP performance gain obtained from the RBR computation operation.
ContributorsMahadevan, Rupa (Author) / Chakrabarti, Chaitali (Thesis advisor) / Kiaei, Sayfe (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. The demands of portable electronics for low power consumption to extend battery life and reduce heat dissipation mandate efficient, high-performance audio amplifiers. The high efficiency of Class D amplifiers (CDAs) makes them particularly attractive for portable applications. The Digital class D amplifier is an interesting solution to increase the efficiency of embedded systems. However, this solution is not good enough in terms of PWM stage linearity and power supply rejection. An efficient control is needed to correct the error sources in order to get a high fidelity sound quality in the whole audio range of frequencies. A fundamental analysis on various error sources due to non idealities in the power stage have been discussed here with key focus on Power supply perturbations driving the Power stage of a Class D Audio Amplifier. Two types of closed loop Digital Class D architecture for PSRR improvement have been proposed and modeled. Double sided uniform sampling modulation has been used. One of the architecture uses feedback around the power stage and the second architecture uses feedback into digital domain. Simulation & experimental results confirm that the closed loop PSRR & PS-IMD improve by around 30-40 dB and 25 dB respectively.
ContributorsChakraborty, Bijeta (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2012
Description
The growth of energy demands in recent years has been increasing faster than the expansion of transmission facility construction. This tendency cooperating with the continuous investing on the renewable energy resources drives the research, development, and construction of HVDC projects to create a more reliable, affordable, and environmentally friendly power grid.
Constructing the hybrid AC-HVDC grid is a significant move in the development of the HVDC techniques; the form of dc system is evolving from the point-to-point stand-alone dc links to the embedded HVDC system and the multi-terminal HVDC (MTDC) system. The MTDC is a solution for the renewable energy interconnections, and the MTDC grids can improve the power system reliability, flexibility in economic dispatches, and converter/cable utilizing efficiencies.
The dissertation reviews the HVDC technologies, discusses the stability issues regarding the ac and HVDC connections, proposes a novel power oscillation control strategy to improve system stability, and develops a nonlinear voltage droop control strategy for the MTDC grid.
To verify the effectiveness the proposed power oscillation control strategy, a long distance paralleled AC-HVDC transmission test system is employed. Based on the PSCAD/EMTDC platform simulation results, the proposed power oscillation control strategy can improve the system dynamic performance and attenuate the power oscillations effectively.
To validate the nonlinear voltage droop control strategy, three droop controls schemes are designed according to the proposed nonlinear voltage droop control design procedures. These control schemes are tested in a hybrid AC-MTDC system. The hybrid AC-MTDC system, which is first proposed in this dissertation, consists of two ac grids, two wind farms and a five-terminal HVDC grid connecting them. Simulation studies are performed in the PSCAD/EMTDC platform. According to the simulation results, all the three design schemes have their unique salient features.
Constructing the hybrid AC-HVDC grid is a significant move in the development of the HVDC techniques; the form of dc system is evolving from the point-to-point stand-alone dc links to the embedded HVDC system and the multi-terminal HVDC (MTDC) system. The MTDC is a solution for the renewable energy interconnections, and the MTDC grids can improve the power system reliability, flexibility in economic dispatches, and converter/cable utilizing efficiencies.
The dissertation reviews the HVDC technologies, discusses the stability issues regarding the ac and HVDC connections, proposes a novel power oscillation control strategy to improve system stability, and develops a nonlinear voltage droop control strategy for the MTDC grid.
To verify the effectiveness the proposed power oscillation control strategy, a long distance paralleled AC-HVDC transmission test system is employed. Based on the PSCAD/EMTDC platform simulation results, the proposed power oscillation control strategy can improve the system dynamic performance and attenuate the power oscillations effectively.
To validate the nonlinear voltage droop control strategy, three droop controls schemes are designed according to the proposed nonlinear voltage droop control design procedures. These control schemes are tested in a hybrid AC-MTDC system. The hybrid AC-MTDC system, which is first proposed in this dissertation, consists of two ac grids, two wind farms and a five-terminal HVDC grid connecting them. Simulation studies are performed in the PSCAD/EMTDC platform. According to the simulation results, all the three design schemes have their unique salient features.
ContributorsYu, Jicheng (Author) / Karady, George G. (Thesis advisor, Committee member) / Qin, Jiangchao (Thesis advisor, Committee member) / Ayyanar, Raja (Committee member) / Holbert, Keith E. (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2017
Description
Li-ion batteries are being used on a large scale varying from consumer electronics to electric vehicles. The key to efficient use of batteries is implementing a well-developed battery management system. Also, there is an opportunity for research for improving the battery performance in terms of size and capacity. For all this it is imperative to develop Li-ion cell model that replicate the performance of a physical cell unit. This report discusses a dual polarization cell model and a battery management system implemented to control the operation of the battery. The Li-ion cell is modelled, and the performance is observed in PLECS environment.
The main aspect of this report studies the viability of Li-ion battery application in Battery Energy Storage System (BESS) in Modular multilevel converter (MMC). MMC-based BESS is a promising solution for grid-level battery energy storage to accelerate utilization and integration of intermittent renewable energy resources, i.e., solar and wind energy. When the battery units are directly integrated in submodules (SMs) without dc-dc interfaced converters, this configuration provides highest system efficiency and lowest cost. However, the lifetime of battery will be affected by the low-frequency components contained in arm currents, which has not been thoroughly investigated. This paper investigates impact of various low-frequency arm-current ripples on lifetime of Li-ion battery cells and evaluate performance of battery charging and discharging in an MMC-BESS without dc-dc interfaced converters.
The main aspect of this report studies the viability of Li-ion battery application in Battery Energy Storage System (BESS) in Modular multilevel converter (MMC). MMC-based BESS is a promising solution for grid-level battery energy storage to accelerate utilization and integration of intermittent renewable energy resources, i.e., solar and wind energy. When the battery units are directly integrated in submodules (SMs) without dc-dc interfaced converters, this configuration provides highest system efficiency and lowest cost. However, the lifetime of battery will be affected by the low-frequency components contained in arm currents, which has not been thoroughly investigated. This paper investigates impact of various low-frequency arm-current ripples on lifetime of Li-ion battery cells and evaluate performance of battery charging and discharging in an MMC-BESS without dc-dc interfaced converters.
ContributorsPuranik, Ishaan (Author) / Qin, Jiangchao (Thesis advisor) / Karady, George G. (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2018
Description
In recent years, wide bandgap (WBG) devices enable power converters with higher power density and higher efficiency. On the other hand, smart grid technologies are getting mature due to new battery technology and computer technology. In the near future, the two technologies will form the next generation of smart grid enabled by WBG devices. This dissertation deals with two applications: silicon carbide (SiC) device used for medium voltage level interface (7.2 kV to 240 V) and gallium nitride (GaN) device used for low voltage level interface (240 V/120 V). A 20 kW solid state transformer (SST) is designed with 6 kHz switching frequency SiC rectifier. Then three robust control design methods are proposed for each of its smart grid operation modes. In grid connected mode, a new LCL filter design method is proposed considering grid voltage THD, grid current THD and current regulation loop robust stability with respect to the grid impedance change. In grid islanded mode, µ synthesis method combined with variable structure control is used to design a robust controller for grid voltage regulation. For grid emergency mode, multivariable controller designed using H infinity synthesis method is proposed for accurate power sharing. Controller-hardware-in-the-loop (CHIL) testbed considering 7-SST system is setup with Real Time Digital Simulator (RTDS). The real TMS320F28335 DSP and Spartan 6 FPGA control board is used to interface a switching model SST in RTDS. And the proposed control methods are tested. For low voltage level application, a 3.3 kW smart grid hardware is built with 3 GaN inverters. The inverters are designed with the GaN device characterized using the proposed multi-function double pulse tester. The inverter is controlled by onboard TMS320F28379D dual core DSP with 200 kHz sampling frequency. Each inverter is tested to process 2.2 kW power with overall efficiency of 96.5 % at room temperature. The smart grid monitor system and fault interrupt devices (FID) based on Arduino Mega2560 are built and tested. The smart grid cooperates with GaN inverters through CAN bus communication. At last, the three GaN inverters smart grid achieved the function of grid connected to islanded mode smooth transition
ContributorsYao, Tong (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Qin, Jiangchao (Committee member) / Tsakalis, Konstantinos (Committee member) / Arizona State University (Publisher)
Created2017
Description
With the increasing penetration of converter interfaced renewable generation into power systems, the structure and behavior of the power system is changing, catalyzing alterations and enhancements in modeling and simulation methods.
This work puts forth a Hybrid Electromagnetic Transient-Transient Stability simulation method implemented using MATLAB and Simulink, to study power electronic based power systems. Hybrid Simulation enables detailed, accurate modeling, along with fast, efficient simulation, on account of the Electromagnetic Transient (EMT) and Transient Stability (TS) simulations respectively. A critical component of hybrid simulation is the interaction between the EMT and TS simulators, established through a well-defined interface technique, which has been explored in detail.
This research focuses on the boundary conditions and interaction between the two simulation models for optimum accuracy and computational efficiency.
A case study has been carried out employing the proposed hybrid simulation method. The test case used is the IEEE 9-bus system, modified to integrate it with a solar PV plant. The validation of the hybrid model with the benchmark full EMT model, along with the analysis of the accuracy and efficiency, has been performed. The steady-state and transient analysis results demonstrate that the performance of the hybrid simulation method is competent. The hybrid simulation technique suitably captures accuracy of EMT simulation and efficiency of TS simulation, therefore adequately representing the behavior of power systems with high penetration of converter interfaced generation.
This work puts forth a Hybrid Electromagnetic Transient-Transient Stability simulation method implemented using MATLAB and Simulink, to study power electronic based power systems. Hybrid Simulation enables detailed, accurate modeling, along with fast, efficient simulation, on account of the Electromagnetic Transient (EMT) and Transient Stability (TS) simulations respectively. A critical component of hybrid simulation is the interaction between the EMT and TS simulators, established through a well-defined interface technique, which has been explored in detail.
This research focuses on the boundary conditions and interaction between the two simulation models for optimum accuracy and computational efficiency.
A case study has been carried out employing the proposed hybrid simulation method. The test case used is the IEEE 9-bus system, modified to integrate it with a solar PV plant. The validation of the hybrid model with the benchmark full EMT model, along with the analysis of the accuracy and efficiency, has been performed. The steady-state and transient analysis results demonstrate that the performance of the hybrid simulation method is competent. The hybrid simulation technique suitably captures accuracy of EMT simulation and efficiency of TS simulation, therefore adequately representing the behavior of power systems with high penetration of converter interfaced generation.
ContributorsAthaide, Denise Maria Christine (Author) / Qin, Jiangchao (Thesis advisor) / Ayyanar, Raja (Committee member) / Wu, Meng (Committee member) / Arizona State University (Publisher)
Created2018
Description
Switching surges are a common type of phenomenon that occur on any sort of power system network. These are more pronounced on long transmission lines and in high voltage substations. The problem with switching surges is encountered when a lot of power is transmitted across a transmission line
etwork, typically from a concentrated generation node to a concentrated load. The problem becomes significantly worse when the transmission line is long and when the voltage levels are high, typically above 400 kV. These overvoltage transients occur following any type of switching action such as breaker operation, fault occurrence/clearance and energization, and they pose a very real danger to weakly interconnected systems. At EHV levels, the insulation coordination of such lines is mainly dictated by the peak level of switching surges, the most dangerous of which include three phase line energization and single-phase reclosing. Switching surges can depend on a number of independent and inter-dependent factors like voltage level, line length, tower construction, location along the line, and presence of other equipment like shunt/series reactors and capacitors.
This project discusses the approaches taken and methods applied to observe and tackle the problems associated with switching surges on a long transmission line. A detailed discussion pertaining to different aspects of switching surges and their effects is presented with results from various studies published in IEEE journals and conference papers. Then a series of simulations are presented to determine an arrangement of substation equipment with respect to incoming transmission lines; that correspond to the lowest surge levels at that substation.
etwork, typically from a concentrated generation node to a concentrated load. The problem becomes significantly worse when the transmission line is long and when the voltage levels are high, typically above 400 kV. These overvoltage transients occur following any type of switching action such as breaker operation, fault occurrence/clearance and energization, and they pose a very real danger to weakly interconnected systems. At EHV levels, the insulation coordination of such lines is mainly dictated by the peak level of switching surges, the most dangerous of which include three phase line energization and single-phase reclosing. Switching surges can depend on a number of independent and inter-dependent factors like voltage level, line length, tower construction, location along the line, and presence of other equipment like shunt/series reactors and capacitors.
This project discusses the approaches taken and methods applied to observe and tackle the problems associated with switching surges on a long transmission line. A detailed discussion pertaining to different aspects of switching surges and their effects is presented with results from various studies published in IEEE journals and conference papers. Then a series of simulations are presented to determine an arrangement of substation equipment with respect to incoming transmission lines; that correspond to the lowest surge levels at that substation.
ContributorsShaikh, Mohammed Mubashir (Author) / Qin, Jiangchao (Thesis advisor) / Heydt, Gerald T (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2018
Description
The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.
ContributorsDesai, Chirag (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2016