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- All Subjects: Silicon-on-insulator technology
- Genre: Academic theses
- Creators: Goryll, Michael
- Status: Published
Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
In the last few years, significant advances in nanofabrication have allowed tailoring of structures and materials at a molecular level enabling nanofabrication with precise control of dimensions and organization at molecular length scales, a development leading to significant advances in nanoscale systems. Although, the direction of progress seems to follow the path of microelectronics, the fundamental physics in a nanoscale system changes more rapidly compared to microelectronics, as the size scale is decreased. The changes in length, area, and volume ratios due to reduction in size alter the relative influence of various physical effects determining the overall operation of a system in unexpected ways. One such category of nanofluidic structures demonstrating unique ionic and molecular transport characteristics are nanopores. Nanopores derive their unique transport characteristics from the electrostatic interaction of nanopore surface charge with aqueous ionic solutions. In this doctoral research cylindrical nanopores, in single and array configuration, were fabricated in silicon-on-insulator (SOI) using a combination of electron beam lithography (EBL) and reactive ion etching (RIE). The fabrication method presented is compatible with standard semiconductor foundries and allows fabrication of nanopores with desired geometries and precise dimensional control, providing near ideal and isolated physical modeling systems to study ion transport at the nanometer level. Ion transport through nanopores was characterized by measuring ionic conductances of arrays of nanopores of various diameters for a wide range of concentration of aqueous hydrochloric acid (HCl) ionic solutions. Measured ionic conductances demonstrated two distinct regimes based on surface charge interactions at low ionic concentrations and nanopore geometry at high ionic concentrations. Field effect modulation of ion transport through nanopore arrays, in a fashion similar to semiconductor transistors, was also studied. Using ionic conductance measurements, it was shown that the concentration of ions in the nanopore volume was significantly changed when a gate voltage on nanopore arrays was applied, hence controlling their transport. Based on the ion transport results, single nanopores were used to demonstrate their application as nanoscale particle counters by using polystyrene nanobeads, monodispersed in aqueous HCl solutions of different molarities. Effects of field effect modulation on particle transition events were also demonstrated.
ContributorsJoshi, Punarvasu (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Thesis advisor) / Spanias, Andreas (Committee member) / Saraniti, Marco (Committee member) / Arizona State University (Publisher)
Created2011
Description
Solid-state nanopore research, used in the field of biomolecule detection and separation, has developed rapidly during the last decade. An electric field generated from the nanopore membrane to the aperture surface by a bias voltage can be used to electrostatically control the transport of charges. This results in ionic current rectification that can be used for applications such as biomolecule filtration and DNA sequencing.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
ContributorsWang, Xiaofeng (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Christen, Jennifer M (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Development of New Front Side Metallization Method of Aluminum Electroplating for Silicon Solar Cell
Description
In this thesis, the methods of aluminum electroplating in an ionic liquid for silicon solar cell front side metallization were studied. It focused on replacing the current silver screen printing with an alternative metallization technology using a low-cost Earth-abundant metal for mass production, due to the high cost and limited availability of silver. A conventional aluminum electroplating method was employed for silicon solar cells fabrication on both p-type and n-type substrates. The highest efficiency of 17.9% was achieved in the n-type solar cell with a rear junction, which is comparable to that of the same structure cell with screen printed silver electrodes from industrial production lines. It also showed better spiking resistant performance than the common structure p-type solar cell. Further efforts were put on the development of a novel light-induced plating of aluminum technique. The aluminum was deposited directly on a silicon substrate without the assistance of a conductive seed layer, thus simplified and reduced the process cost. The plated aluminum has good adhesion to the silicon surface with the resistivity as low as 4×10–6 -cm. A new demo tool was designed and set up for the light-induced plating experiment, aiming to utilize this technique in large-size solar cells fabrication and mass production. Besides the metallization methods, a comprehensive sensitivity analysis for the efficiency dispersion in the production of crystalline-Si solar cells was presented based on numerical simulations. Temperature variation in the diffusion furnace was the most significant cause of the efficiency dispersion. It was concluded that a narrow efficiency range of ±0.5% absolute is achievable if the emitter diffusion temperature is confined to a 13˚C window, while other cell parameters vary within their normal windows. Possible methods to minimize temperature variation in emitter diffusion were proposed.
ContributorsWang, Laidong (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Kozicki, Michael (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2018
Description
ABSTRACT
Autonomous smart windows may be integrated with a stack of active components, such as electrochromic devices, to modulate the opacity/transparency by an applied voltage. Here, we describe the processing and performance of two classes of visibly-transparent photovoltaic materials, namely inorganic (ZnO thin film) and fully organic (PCDTBT:PC70BM), for integration with electrochromic stacks.
Sputtered ZnO (2% Mn) films on ITO, with transparency in the visible range, were used to fabricate metal-semiconductor (MS), metal-insulator-semiconductor (MIS), and p-i-n heterojunction devices, and their photovoltaic conversion under ultraviolet (UV) illumination was evaluated with and without oxygen plasma-treated surface electrodes (Au, Ag, Al, and Ti/Ag). The MS Schottky parameters were fitted against the generalized Bardeen model to obtain the density of interface states (Dit ≈ 8.0×1011 eV−1cm−2) and neutral level (Eo ≈ -5.2 eV). These devices exhibited photoconductive behavior at λ = 365 nm, and low-noise Ag-ZnO detectors exhibited responsivity (R) and photoconductive gain (G) of 1.93×10−4 A/W and 6.57×10−4, respectively. Confirmed via matched-pair analysis, post-metallization, oxygen plasma treatment of Ag and Ti/Ag electrodes resulted in increased Schottky barrier heights, which maximized with a 2 nm SiO2 electron blocking layer (EBL), coupled with the suppression of recombination at the metal/semiconductor interface and blocking of majority carriers. For interdigitated devices under monochromatic UV-C illumination, the open-circuit voltage (Voc) was 1.2 V and short circuit current density (Jsc), due to minority carrier tunneling, was 0.68 mA/cm2.
A fully organic bulk heterojunction photovoltaic device, composed of poly[N-9’-heptadecanyl-2,7-carbazole-alt-5,5-(4’,7’-di-2-thienyli2’,1’,3’-benzothiadiazole)]:phenyl-C71-butyric-acidmethyl (PCDTBT:PC70BM), with corresponding electron and hole transport layers, i.e., LiF with Al contact and conducting
on-conducting (nc) PEDOT:PSS (with ITO/PET or Ag nanowire/PDMS contacts; the illuminating side), respectively, was developed. The PCDTBT/PC70BM/PEDOT:PSS(nc)/ITO/PET stack exhibited the highest performance: power conversion efficiency (PCE) ≈ 3%, Voc = 0.9V, and Jsc ≈ 10-15 mA/cm2. These stacks exhibited high visible range transparency, and provided the requisite power for a switchable electrochromic stack having an inkjet-printed, optically-active layer of tungsten trioxide (WO3), peroxo-tungstic acid dihydrate, and titania (TiO2) nano-particle-based blend. The electrochromic stacks (i.e., PET/ITO/LiClO4/WO3 on ITO/PET and Ag nanowire/PDMS substrates) exhibited optical switching under external bias from the PV stack (or an electrical outlet), with 7 s coloration time, 8 s bleaching time, and 0.36-0.75 optical modulation at λ = 525 nm. The devices were paired using an Internet of Things controller that enabled wireless switching.
Autonomous smart windows may be integrated with a stack of active components, such as electrochromic devices, to modulate the opacity/transparency by an applied voltage. Here, we describe the processing and performance of two classes of visibly-transparent photovoltaic materials, namely inorganic (ZnO thin film) and fully organic (PCDTBT:PC70BM), for integration with electrochromic stacks.
Sputtered ZnO (2% Mn) films on ITO, with transparency in the visible range, were used to fabricate metal-semiconductor (MS), metal-insulator-semiconductor (MIS), and p-i-n heterojunction devices, and their photovoltaic conversion under ultraviolet (UV) illumination was evaluated with and without oxygen plasma-treated surface electrodes (Au, Ag, Al, and Ti/Ag). The MS Schottky parameters were fitted against the generalized Bardeen model to obtain the density of interface states (Dit ≈ 8.0×1011 eV−1cm−2) and neutral level (Eo ≈ -5.2 eV). These devices exhibited photoconductive behavior at λ = 365 nm, and low-noise Ag-ZnO detectors exhibited responsivity (R) and photoconductive gain (G) of 1.93×10−4 A/W and 6.57×10−4, respectively. Confirmed via matched-pair analysis, post-metallization, oxygen plasma treatment of Ag and Ti/Ag electrodes resulted in increased Schottky barrier heights, which maximized with a 2 nm SiO2 electron blocking layer (EBL), coupled with the suppression of recombination at the metal/semiconductor interface and blocking of majority carriers. For interdigitated devices under monochromatic UV-C illumination, the open-circuit voltage (Voc) was 1.2 V and short circuit current density (Jsc), due to minority carrier tunneling, was 0.68 mA/cm2.
A fully organic bulk heterojunction photovoltaic device, composed of poly[N-9’-heptadecanyl-2,7-carbazole-alt-5,5-(4’,7’-di-2-thienyli2’,1’,3’-benzothiadiazole)]:phenyl-C71-butyric-acidmethyl (PCDTBT:PC70BM), with corresponding electron and hole transport layers, i.e., LiF with Al contact and conducting
on-conducting (nc) PEDOT:PSS (with ITO/PET or Ag nanowire/PDMS contacts; the illuminating side), respectively, was developed. The PCDTBT/PC70BM/PEDOT:PSS(nc)/ITO/PET stack exhibited the highest performance: power conversion efficiency (PCE) ≈ 3%, Voc = 0.9V, and Jsc ≈ 10-15 mA/cm2. These stacks exhibited high visible range transparency, and provided the requisite power for a switchable electrochromic stack having an inkjet-printed, optically-active layer of tungsten trioxide (WO3), peroxo-tungstic acid dihydrate, and titania (TiO2) nano-particle-based blend. The electrochromic stacks (i.e., PET/ITO/LiClO4/WO3 on ITO/PET and Ag nanowire/PDMS substrates) exhibited optical switching under external bias from the PV stack (or an electrical outlet), with 7 s coloration time, 8 s bleaching time, and 0.36-0.75 optical modulation at λ = 525 nm. The devices were paired using an Internet of Things controller that enabled wireless switching.
ContributorsAzhar, Ebraheem (Author) / Yu, Hongbin (Thesis advisor) / Dey, Sandwip (Thesis advisor) / Goryll, Michael (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2018
Description
To date, the most popular and dominant material for commercial solar cells is
crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out
of all commercial solar cells. Although the potential of crystalline-Si solar cells in
supplying energy demands is enormous, their future growth will likely be constrained
by two major bottlenecks. The first is the high electricity input to produce
crystalline-Si solar cells and modules, and the second is the limited supply of silver
(Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching
terawatt-scale deployment, which means the electricity produced by crystalline-Si
solar cells would never fulfill a noticeable portion of our energy demands in the future.
In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al)
electroplating has been developed as an alternative metallization technique in the
fabrication of crystalline-Si solar cells. The plating is carried out in a
near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been
found that dense, adherent Al deposits with resistivity in the high 10^–6 ohm-cm range
can be reproducibly obtained directly on Si substrates and nickel seed layers. An
all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al
back electrode, has been successfully demonstrated based on commercial p-type
monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further
optimization of the cell fabrication process, in particular a suitable patterning
technique for the front silicon nitride layer, is expected to increase the efficiency of
the cell to ~18%. This shows the potential of Al electroplating in cell metallization is
promising and replacing Ag with Al as the front finger electrode is feasible.
crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out
of all commercial solar cells. Although the potential of crystalline-Si solar cells in
supplying energy demands is enormous, their future growth will likely be constrained
by two major bottlenecks. The first is the high electricity input to produce
crystalline-Si solar cells and modules, and the second is the limited supply of silver
(Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching
terawatt-scale deployment, which means the electricity produced by crystalline-Si
solar cells would never fulfill a noticeable portion of our energy demands in the future.
In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al)
electroplating has been developed as an alternative metallization technique in the
fabrication of crystalline-Si solar cells. The plating is carried out in a
near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been
found that dense, adherent Al deposits with resistivity in the high 10^–6 ohm-cm range
can be reproducibly obtained directly on Si substrates and nickel seed layers. An
all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al
back electrode, has been successfully demonstrated based on commercial p-type
monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further
optimization of the cell fabrication process, in particular a suitable patterning
technique for the front silicon nitride layer, is expected to increase the efficiency of
the cell to ~18%. This shows the potential of Al electroplating in cell metallization is
promising and replacing Ag with Al as the front finger electrode is feasible.
ContributorsSun, Wen-Cheng (Author) / Tao, Meng (Thesis advisor) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
Description
A Microbial fuel cell (MFC) is a bio-inspired carbon-neutral, renewable electrochemical converter to extract electricity from catabolic reaction of micro-organisms. It is a promising technology capable of directly converting the abundant biomass on the planet into electricity and potentially alleviate the emerging global warming and energy crisis. The current and power density of MFCs are low compared with conventional energy conversion techniques. Since its debut in 2002, many studies have been performed by adopting a variety of new configurations and structures to improve the power density. The reported maximum areal and volumetric power densities range from 19 mW/m2 to 1.57 W/m2 and from 6.3 W/m3 to 392 W/m3, respectively, which are still low compared with conventional energy conversion techniques. In this dissertation, the impact of scaling effect on the performance of MFCs are investigated, and it is found that by scaling down the characteristic length of MFCs, the surface area to volume ratio increases and the current and power density improves. As a result, a miniaturized MFC fabricated by Micro-Electro-Mechanical System(MEMS) technology with gold anode is presented in this dissertation, which demonstrate a high power density of 3300 W/m3. The performance of the MEMS MFC is further improved by adopting anodes with higher surface area to volume ratio, such as carbon nanotube (CNT) and graphene based anodes, and the maximum power density is further improved to a record high power density of 11220 W/m3. A novel supercapacitor by regulating the respiration of the bacteria is also presented, and a high power density of 531.2 A/m2 (1,060,000 A/m3) and 197.5 W/m2 (395,000 W/m3), respectively, are marked, which are one to two orders of magnitude higher than any previously reported microbial electrochemical techniques.
ContributorsRen, Hao (Author) / Chae, Junseok (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Phillips, Stephen (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250°C.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235°C.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
ContributorsSummers, Nicholas, M.S (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010