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- Creators: Goryll, Michael
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Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
While the piezoelectric effect has been around for some time, it has only recently caught interest as a potential sustainable energy harvesting device. Piezoelectric energy harvesting has been developed for shoes and panels, but has yet to be integrated into a marketable bicycle tire. For this thesis, the development and feasibility of a piezoelectric tire was done. This includes the development of a circuit that incorporates piezoceramic elements, energy harvesting circuitry, and an energy storage device. A single phase circuit was designed using an ac-dc diode rectifier. An electrolytic capacitor was used as the energy storage device. A financial feasibility was also done to determine targets for manufacturing cost and sales price. These models take into account market trends for high performance tires, economies of scale, and the possibility of government subsidies. This research will help understand the potential for the marketability of a piezoelectric energy harvesting tire that can create electricity for remote use. This study found that there are many obstacles that must be addressed before a piezoelectric tire can be marketed to the general public. The power output of this device is miniscule compared to an alkaline battery. In order for this device to approach the power output of an alkaline battery the weight of the device would also become an issue. Additionally this device is very costly compared to the average bicycle tire. Lastly, this device is extreme fragile and easily broken. In order for this device to become marketable the issues of power output, cost, weight, and durability must all be successfully overcome.
ContributorsMalotte, Christopher (Author) / Madakannan, Arunachalanadar (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
Potential induced degradation (PID) due to high system voltages is one of the major degradation mechanisms in photovoltaic (PV) modules, adversely affecting their performance due to the combined effects of the following factors: system voltage, superstrate/glass surface conductivity, encapsulant conductivity, silicon nitride anti-reflection coating property and interface property (glass/encapsulant; encapsulant/cell; encapsulant/backsheet). Previous studies carried out at ASU's Photovoltaic Reliability Laboratory (ASU-PRL) showed that only negative voltage bias (positive grounded systems) adversely affects the performance of commonly available crystalline silicon modules. In previous studies, the surface conductivity of the glass surface was obtained using either conductive carbon layer extending from the glass surface to the frame or humidity inside an environmental chamber. This thesis investigates the influence of glass surface conductivity disruption on PV modules. In this study, conductive carbon was applied only on the module's glass surface without extending to the frame and the surface conductivity was disrupted (no carbon layer) at 2cm distance from the periphery of frame inner edges. This study was carried out under dry heat at two different temperatures (60 °C and 85 °C) and three different negative bias voltages (-300V, -400V, and -600V). To replicate closeness to the field conditions, half of the selected modules were pre-stressed under damp heat for 1000 hours (DH 1000) and the remaining half under 200 hours of thermal cycling (TC 200). When the surface continuity was disrupted by maintaining a 2 cm gap from the frame to the edge of the conductive layer, as demonstrated in this study, the degradation was found to be absent or negligibly small even after 35 hours of negative bias at elevated temperatures. This preliminary study appears to indicate that the modules could become immune to PID losses if the continuity of the glass surface conductivity is disrupted at the inside boundary of the frame. The surface conductivity of the glass, due to water layer formation in a humid condition, close to the frame could be disrupted just by applying a water repelling (hydrophobic) but high transmittance surface coating (such as Teflon) or modifying the frame/glass edges with water repellent properties.
ContributorsTatapudi, Sai Ravi Vasista (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT As the use of photovoltaic (PV) modules in large power plants continues to increase globally, more studies on degradation, reliability, failure modes, and mechanisms of field aged modules are needed to predict module life expectancy based on accelerated lifetime testing of PV modules. In this work, a 26+ year old PV power plant in Phoenix, Arizona has been evaluated for performance, reliability, and durability. The PV power plant, called Solar One, is owned and operated by John F. Long's homeowners association. It is a 200 kWdc, standard test conditions (STC) rated power plant comprised of 4000 PV modules or frameless laminates, in 100 panel groups (rated at 175 kWac). The power plant is made of two center-tapped bipolar arrays, the north array and the south array. Due to a limited time frame to execute this large project, this work was performed by two masters students (Jonathan Belmont and Kolapo Olakonu) and the test results are presented in two masters theses. This thesis presents the results obtained on the south array and the other thesis presents the results obtained on the north array. Each of these two arrays is made of four sub arrays, the east sub arrays (positive and negative polarities) and the west sub arrays (positive and negative polarities), making up eight sub arrays. The evaluation and analyses of the power plant included in this thesis consists of: visual inspection, electrical performance measurements, and infrared thermography. A possible presence of potential induced degradation (PID) due to potential difference between ground and strings was also investigated. Some installation practices were also studied and found to contribute to the power loss observed in this investigation. The power output measured in 2011 for all eight sub arrays at STC is approximately 76 kWdc and represents a power loss of 62% (from 200 kW to 76 kW) over 26+ years. The 2011 measured power output for the four south sub arrays at STC is 39 kWdc and represents a power loss of 61% (from 100 kW to 39 kW) over 26+ years. Encapsulation browning and non-cell interconnect ribbon breakages were determined to be the primary causes for the power loss.
ContributorsOlakonu, Kolapo (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
With the progression of different industries moving away from employing secretaries for business professionals and professors, there exists a void in the area of personal assistance. This problem has existing solutions readily available to replace this service, i.e. secretary or personal assistant, tend to range from expensive and useful to inexpensive and not efficient. This leaves a low cost niche into the market of a virtual office assistant or manager to display messages and to help direct people in obtaining contact information. The development of a low cost solution revolves around the software needed to solve the various problems an accessible and user friendly Virtual Interface in which the owner of the Virtual Office Manager/Assistant can communicate to colleagues who are at standby outside of the owner's office and vice versa. This interface will be allowing the owner to describe the status pertaining to their absence or any other message sent to the interface. For example, the status of the owner's work commute can be described with a simple "Running Late" phrase or a message like "Busy come back in 10 minutes". In addition, any individual with an interest to these entries will have the opportunity to respond back because the device will provide contact information. When idle, the device will show supplemental information such as the owner's calendar and name. The scope of this will be the development and testing of solutions to achieve these goals.
ContributorsOffenberger, Spencer Eliot (Author) / Kozicki, Michael (Thesis director) / Goryll, Michael (Committee member) / Electrical Engineering Program (Contributor) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
Interdigitated back contact (IBC) solar cells have achieved the highest single junction silicon wafer-based solar cell power conversion efficiencies reported to date. This thesis is about the fabrication of a high-efficiency silicon heterojunction IBC solar cell for potential use as the bottom cell for a 3-terminal lattice-matched dilute-nitride Ga (In)NP(As)/Si monolithic tandem solar cell. An effective fabrication process has been developed and the process challenges related to open circuit voltage (Voc), series resistance (Rs), and fill factor (FF) are experimentally analyzed. While wet etching, the sample lost the initial passivation, and by changing the etchant solution and passivation process, the voltage at maximum power recovered to an initial value of over 710 mV before metallization. The factors reducing the series resistance loss in IBC cells were also studied. One of these factors was the Indium Tin Oxide (ITO) sputtering parameters, which impact the conductivity of the ITO layer and transport across the a-Si:H/ITO interface. For the standard recipe, the chamber pressure was 3.5 mTorr with no oxygen partial pressure, and the thickness of the ITO layer in contact with the a-Si:H layers, was optimized to 150 nm. The patterning method for the metal contacts and final annealing also change the contact resistance of the base and emitter stack layers. The final annealing step is necessary to recover the sputtering damage; however, the higher the annealing time the higher the final IBC series resistance. The best efficiency achieved was 19.3% (Jsc = 37 mA/cm2, Voc = 691 mV, FF = 71.7%) on 200 µm thick 1-15 Ω-cm n-type CZ C-Si with a designated area of 4 cm2.
ContributorsMoeini Rizi, Mansoure (Author) / Goodnick, Stephen (Thesis advisor) / Honsberg, Christina (Committee member) / Goryll, Michael (Committee member) / Smith, David (Committee member) / Bowden, Stuart (Committee member) / Arizona State University (Publisher)
Created2022
Description
In-field characterization of photovoltaics is crucial to understanding performance and degradation mechanisms, subsequently improving overall reliability and lifespans. Current outdoor characterization is often limited by logistical difficulties, variable weather, and requirements to measure during peak production hours. It becomes a challenge to find a characterization technique that is affordable with a low impact on system performance while still providing useful device parameters. For added complexity, this characterization technique must have the ability to scale for implementation in large powerplant applications. This dissertation addresses some of the challenges of outdoor characterization by expanding the knowledge of a well-known indoor technique referred to as Suns-VOC. Suns-VOC provides a pseudo current-voltage curve that is free of any effects from series resistance. Device parameters can be extracted from this pseudo I-V curve, allowing for subsequent degradation analysis. This work introduces how to use Suns-VOC outdoors while normalizing results based on the different effects of environmental conditions. This technique is validated on single-cells, modules, and small arrays with accuracies capable of measuring yearly degradation. An adaptation to Suns-VOC, referred to as Suns-Voltage-Resistor (Suns-VR), is also introduced to complement the results from Suns-VOC. This work can potentially be used to provide a diagnostic tool for outdoor characterization in various applications, including residential, commercial, and industrial PV systems.
ContributorsKillam, Alexander Cameron (Author) / Bowden, Stuart G (Thesis advisor) / Goryll, Michael (Committee member) / Augusto, Andre (Committee member) / Rand, James (Committee member) / Arizona State University (Publisher)
Created2022
Description
To keep up with the increasing demand for solar energy, higher efficiencies are necessary while keeping cost at a minimum. The easiest theoretical way to achieve that is using silicon-based multi-junction solar cells. However, there are major challenges in effectively implementing such a system. Much work has been done recently to integrate III-V with Si for multi-junction solar cell purposes. The focus of this paper is to explore GaP-based dilute nitrides as a possible top cell candidate for Si-based multi-junctions. The direct growth of dilute nitrides in a lattice-matched configuration epitaxially in literature is reviewed. The problems associated with such growths are outlined and pathways to mitigate these problems are presented. The need for a GaP buffer layer between the dilute nitride film and Si is established. Defects in GaP/Si system are explored in detail and a study on pit formation during such growth is performed. Effective suppression of pits in GaP surface grown on Si is achieved. Issues facing GaP-based dilute nitrides in terms of material properties are outlined. Review of these challenges is done and some possible future areas of interest to improve material quality are established. Finally, the growth process of dilute nitrides using Molecular Beam Epitaxy tool is explained. Results for GaNP grown on Si pre and post growth treatments are detailed.
ContributorsMurali, Srinath (Author) / Honsberg, Christiana (Thesis advisor) / Goodnick, Stephen (Committee member) / King, Richard (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022
Description
In this dissertation, the nanofabrication process is characterized for fabrication of nanostructure on surface of silicon and gallium phosphide using silica nanosphere lithography (SNL) and metal assisted chemical etching (MACE) process. The SNL process allows fast process time and well defined silica nanosphere monolayer by spin-coating process after mixing N,N-dimethyl-formamide (DMF) solvent. The MACE process achieves the high aspect ratio structure fabrication using the reaction between metal and wet chemical. The nanostructures are fabricated on Si surface for enhanced light management, but, without proper surface passivation those gains hardly impact the performance of the solar cell. The surface passivation of nanostructures is challenging, not only due to larger surface areas and aspect ratios, but also has a direct result of the nanofabrication processes. In this research, the surface passivation of silicon nanostructures is improved by modifying the silica nanosphere lithography (SNL) and the metal assisted chemical etching (MACE) processes, frequently used to fabricate nanostructures. The implementation of a protective silicon oxide layer is proposed prior to the lithography process to mitigate the impact of the plasma etching during the SNL. Additionally, several adhesion layers are studied, chromium (Cr), nickel (Ni) and titanium (Ti) with gold (Au), used in the MACE process. The metal contamination is one of main damage and Ti makes the mitigation of metal contamination. Finally, a new chemical etching step is introduced, using potassium hydroxide at room temperature, to smooth the surface of the nanostructures after the MACE process. This chemical treatment allows to improve passivation by surface area control and removing surface defects. In this research, I demonstrate the Aluminum Oxide (Al2O3) passivation on nanostructure using atomic layer deposition (ALD) process. 10nm of Al2O3 layer makes effective passivation on nanostructure with optimized post annealing in forming gas (N2/H2) environment. However, 10nm thickness is not suitable for hetero structure because of carrier transportation. For carrier transportation, ultrathin Al2O3 (≤ 1nm) layer is used for passivation, but effective passivation is not achieved because of insufficient hydrogen contents. This issue is solved to use additional ultrathin SiO2 (1nm) below Al2O3 layer and hydrogenation from doped a-Si:H.
Moreover, the nanostructure is creased on gallium phosphide (GaP) by SNL and MACE process. The fabrication process is modified by control of metal layer and MACE solution.
ContributorsKim, Sangpyeong (Author) / Honsberg, Christiana (Thesis advisor) / Bowden, Stuart (Committee member) / Goryll, Michael (Committee member) / Augusto, Andre (Committee member) / Arizona State University (Publisher)
Created2021