Full metadata
Title
RISC-V Exceptions and Interrupts
Description
RISC-V is an open-source processor architecture developed by students and faculty at the University of California at Berkeley. This document explores RISC-V exceptions and interrupts by clarifying how this computer architecture handles traps. The document defines the different exceptions and interrupts outlined in the RISC-V architecture and explains the different registers that are used by the trap handler. This document also briefly addresses concepts outside the purview of the RISC-V ISA like interrupt controllers which are important for understanding how these external events interact with the processor hardware.
Date Created
2020-12
Contributors
- Keller, Sean Richard (Author)
- Abraham, Seth (Thesis director)
- Brunhaver, John (Committee member)
- Electrical Engineering Program (Contributor)
- Barrett, The Honors College (Contributor)
Topical Subject
Resource Type
Extent
17 pages
Language
Copyright Statement
In Copyright
Primary Member of
Series
Academic Year 2020-2021
Handle
https://hdl.handle.net/2286/R.I.62419
Level of coding
minimal
Cataloging Standards
System Created
- 2020-11-11 11:00:12
System Modified
- 2021-08-11 04:09:57
- 2 years 8 months ago
Additional Formats