Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
Displaying 231 - 240 of 243
Filtering by
- Creators: Bakkaloglu, Bertan
- Creators: Turaga, Pavan
ContributorsHaagen, Jordan (Author) / Turaga, Pavan (Thesis director) / Drummond Otten, Caitlin (Committee member) / Barrett, The Honors College (Contributor) / Arts, Media and Engineering Sch T (Contributor)
Created2022-05
Description
Oftentimes, patients struggle to accurately describe their symptoms to medical professionals, which produces erroneous diagnoses, delaying and preventing treatment. My app, Augnosis, will streamline constructive communication between patient and doctor, and allow for more accurate diagnoses. The goal of this project was to create an app capable of gathering data on visual symptoms of facial acne and categorizing it to differentiate between diagnoses using image recognition and identification. “Augnosis”, is a combination of the words “Augmented Reality” and “Self-Diagnosis”, the former being the medium in which it is immersed and the latter detailing its functionality.
ContributorsGoyal, Nandika (Author) / Johnson, Mina (Thesis director) / Bryan, Chris (Committee member) / Turaga, Pavan (Committee member) / Barrett, The Honors College (Contributor) / Computer Science and Engineering Program (Contributor)
Created2022-05
Description
ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator.
ContributorsSwaminathan, Visu Vaithiyanathan (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis presents robust and novel solutions using knowledge distillation with geometric approaches and multimodal data that can address the current challenges in deep learning, providing a comprehensive understanding of the learning process involved in knowledge distillation. Deep learning has attained significant success in various applications, such as health and wellness promotion, smart homes, and intelligent surveillance. In general, stacking more layers or increasing the number of trainable parameters causes deep networks to exhibit improved performance. However, this causes the model to become large, resulting in an additional need for computing and power resources for training, storage, and deployment. These are the core challenges in incorporating such models into small devices with limited power and computational resources. In this thesis, robust solutions aimed at addressing the aforementioned challenges are presented. These proposed methodologies and algorithmic contributions enhance the performance and efficiency of deep learning models. The thesis encompasses a comprehensive exploration of knowledge distillation, an approach that holds promise for creating compact models from high-capacity ones, while preserving their performance. This exploration covers diverse datasets, including both time series and image data, shedding light on the pivotal role of augmentation methods in knowledge distillation. The effects of these methods are rigorously examined through empirical experiments. Furthermore, the study within this thesis delves into the efficient utilization of features derived from two different teacher models, each trained on dissimilar data representations, including time-series and image data. Through these investigations, I present novel approaches to knowledge distillation, leveraging geometric techniques for the analysis of multimodal data. These solutions not only address real-world challenges but also offer valuable insights and recommendations for modeling in new applications.
ContributorsJeon, Eunsom (Author) / Turaga, Pavan (Thesis advisor) / Li, Baoxin (Committee member) / Lee, Hyunglae (Committee member) / Jayasuriya, Suren (Committee member) / Arizona State University (Publisher)
Created2023
Description
Impedance is one of the fundamental properties of electrical components, materials, and waves. Therefore, impedance measurement and monitoring have a wide range of applications. The multi-port technique is a natural candidate for impedance measurement and monitoring due to its low overhead and ease of implementation for Built-in Self-Test (BIST) applications. The multi-port technique can measure complex reflection coefficients, thus impedance, by using scalar measurements provided by the power detectors. These power detectors are strategically placed on different points (ports) of a passive network to produce unique solution. Impedance measurement and monitoring is readily deployed on mobile phone radio-frequency (RF) front ends, and are combined with antenna tuners to boost the signal reception capabilities of phones. These sensors also can be used in self-healing circuits to improve their yield and performance under process, voltage, and temperature variations. Even though, this work is preliminary interested in low-overhead impedance measurement for RF circuit applications, the proposed methods can be used in a wide variety of metrology applications where impedance measurements are already used. Some examples of these applications include determining material properties, plasma generation, and moisture detection. Additionally, multi-port applications extend beyond the impedance measurement. There are applications where multi-ports are used as receivers for communication systems, RADARs, and remote sensing applications. The multi-port technique generally requires a careful design of the testing structure to produce a unique solution from power detector measurements. It also requires the use of nonlinear solvers during calibration, and depending on calibration procedure, measurement. The use of nonlinear solvers generates issues for convergence, computational complexity, and resources needed for carrying out calibrations and measurements in a timely manner. In this work, using periodic structures, a structure where a circuit block repeats itself, for multi-port measurements is proposed. The periodic structures introduce a new constraint that simplifies the multi-port theory and leads to an explicit calibration and measurement procedure. Unlike the existing calibration procedures which require at least five loads and various constraints on the load for explicit solution, the proposed method can use three loads for calibration. Multi-ports built with periodic structures will always produce a unique measurement result. This leads to increased bandwidth of operation and simplifies design procedure. The efficacy of the method demonstrated in two embodiments.
In the first embodiment, a multi-port is directly embedded into a matching network to measure impedance of the load.
In the second embodiment, periodic structures are used to compare two loads without requiring any calibration.
ContributorsAvci, Muslum Emir (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Trichopoulos, Georgios (Committee member) / Arizona State University (Publisher)
Created2023
Description
This work presents two balanced power amplifier (PA) architectures, one at X-band and the other at K-band. The presented balanced PAs are designed for use in small satellite and cube satellite applications.The presented X-band PA employs wideband hybrid couplers to split input power to two commercial off-the-shelf (COTS) Gallium Nitride (GaN) monolithic microwave integrated circuit (MMIC) PAs and combine their output powers. The presented X-band balanced PA manufactured on a Rogers 4003C substrate yields increased small signal gain and saturated output power under continuous wave (CW) operation compared to the single MMIC PA used in the design under pulsed operation. The presented PA operates from 7.5 GHz to 11.5 GHz, has a maximum small signal gain of 36.3 dB, a maximum saturated power out of 40.0 dBm, and a maximum power added efficiency (PAE) of 38%.
Both a Wilkinson and a Gysel splitter and combiner are designed for use at K-band and their performance is compared. The presented K-band balanced PA uses Gysel power dividers and combiners with a GaN MMIC PA that is soon to be released in production.
ContributorsPearson, Katherine Elizabeth (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2023
Description
Generative models are deep neural network-based models trained to learn the underlying distribution of a dataset. Once trained, these models can be used to sample novel data points from this distribution. Their impressive capabilities have been manifested in various generative tasks, encompassing areas like image-to-image translation, style transfer, image editing, and more. One notable application of generative models is data augmentation, aimed at expanding and diversifying the training dataset to augment the performance of deep learning models for a downstream task. Generative models can be used to create new samples similar to the original data but with different variations and properties that are difficult to capture with traditional data augmentation techniques. However, the quality, diversity, and controllability of the shape and structure of the generated samples from these models are often directly proportional to the size and diversity of the training dataset. A more extensive and diverse training dataset allows the generative model to capture overall structures present in the data and generate more diverse and realistic-looking samples.
In this dissertation, I present innovative methods designed to enhance the robustness and controllability of generative models, drawing upon physics-based, probabilistic, and geometric techniques. These methods help improve the generalization and controllability of the generative model without necessarily relying on large training datasets. I enhance the robustness of generative models by integrating classical geometric moments for shape awareness and minimizing trainable parameters. Additionally, I employ non-parametric priors for the generative model's latent space through basic probability and optimization methods to improve the fidelity of interpolated images. I adopt a hybrid approach to address domain-specific challenges with limited data and controllability, combining physics-based rendering with generative models for more realistic results.
These approaches are particularly relevant in industrial settings, where the training datasets are small and class imbalance is common. Through extensive experiments on various datasets, I demonstrate the effectiveness of the proposed methods over conventional approaches.
ContributorsSingh, Rajhans (Author) / Turaga, Pavan (Thesis advisor) / Jayasuriya, Suren (Committee member) / Berisha, Visar (Committee member) / Fazli, Pooyan (Committee member) / Arizona State University (Publisher)
Created2023
Description
In this dissertation, enhanced coherent detection of terahertz (THz) radiation is presented for Silicon integrated circuits (ICs). In general THz receivers implemented in silicon technologies face a challenge due to the high noise figure (NF) of the low noise amplifier (LNA) and low conversion gain of the radio frequency (RF) mixers. Moreover, issues with implementing local oscillators (LOs) further compound these challenges, including power driving mixes, distribution networks, and overall power consumption, particularly for large-scale arrays. To address these inherent obstacles, two notable cases of enhancing THz receiver performance are presented. In the Sideband Separation Receiver (SSR) for space-borne applications is introduced. Implemented in SiGe BiCMOS technology this broadband SSR boasts a high Image Rejection Ratio (IRR) exceeding 20 dB across 220 – 320 GHz. Employing a modified Weaver architecture, optimized for simultaneous spectral line observation, it utilizes an I/Q double down-conversion, pushing the technological boundaries of silicon and enabling large-scale focal plane array (FPA) deployment in space. Notably, the use of a sub-harmonic down-conversion mixer (SHM) significantly reduces LO power generation challenges, enhancing scalability while maintaining minimal NF.
In the 4x4 FPA active THz imager, a dual-polarized patch antenna operating at 420 GHz utilizes orthogonal polarization for RF and LO signals, coupled with a coherent homodyne power detector. Realized in 0.13µm SiGe HBT technology, the power detector is co-designing with the antenna to ensure minimal crosstalk and achieving -30dB cross-polarization isolation. Illumination of the LO enhances power detector performance without on-chip routing complexities, enabling scalability to 1K pixel THz imagers. Each pixel achieves a Noise-Equivalent Power (NEP) of 1 pW/√Hz at 420 GHz, and integration with a readout and digital filter ensures high dynamic range.
Furthermore, this study explores radiation hardening techniques to mitigate single-event effects (SEEs) in high-frequency receivers operating in space. Leveraging a W-band receiver in 90 nm SiGe BiCMOS technology, matching considerations and diverse modes of operation are employed to reduce SEE susceptibility. Transient current pulse modeling, validated through TCAD simulations, demonstrates the effectiveness of proposed techniques in substantially mitigating SETs within the proposed radiation-hardened-by-design (RHBD) receiver front-end.
ContributorsAl Seragi, Ebrahim (Author) / Zeinolabedinzadeh, Saeed (Thesis advisor) / Trichopoulos, Georgios (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2024
Description
Recent advancements in communication standards, such as 5G demand transmitter hardware to support high data rates with high energy efficiency. With the revolution of communication standards, modulation schemes have become more complex and require high peak-to-average (PAPR) signals. In wireless transceiver hardware, the power amplifier (PA) consumes most of the transceiver’s DC power and is typically the bottleneck for transmitter linearity. Therefore, the transmitter’s performance directly depends on the PA. To support high PAPR signals, the PA must operate efficiently at its saturated and backoff output power. Maintaining high efficiency at both peak and backoff output power is challenging. One effective technique for addressing this problem is load modulation. Some of the prominent load-modulated PA architectures are outphasing PAs, load-modulated balanced amplifiers (LMBA), envelope elimination and restoration (EER), envelope tracking (ET), Doherty power amplifiers (DPA), and polar transmitters. Amongst them, the DPA is the most popular for infrastructure applications due to its simpler architecture compared to other techniques and linearizability with digital pre-distortion (DPD). Another crucial characteristic of progressing communication standards is wide signal bandwidths. High-efficiency power amplifiers like class J/F/F-1 and load-modulated PAs like the DPA exhibit narrowband performance because the amplifiers require precise output impedance terminations. Therefore, it is equally essential to develop adaptable PA solutions to process radio frequency (RF) signals with wide bandwidths. To support modern and future cellular infrastructure, RF PAs need to be innovated to increase the backoff power efficiency by two times or more and support ten times or more wider bandwidths than current state-of-the-art PAs. This work presents five RF PA analyses and implementations to support future wireless communications transmitter hardware. Chapter 2 presents an optimized output-matching network analysis and design to achieve extended output power backoff of the DPA. Chapters 3 and 4 unveil two bandwidth enhancement techniques for the DPA while maintaining extended output power backoff. Chapter 5 exhibits a dual-band hybrid mode PA design targeted for wideband applications. Chapter 6 presents a built-in self-test circuit integrated into a PA for output impedance monitoring. This can alleviate the PA performance degradation due to the variation in the PA's output load over frequency, process, and aging. All RF PAs in this dissertation are implemented using Gallium Nitride (GaN)-based high electron mobility transistors (HEMT), and the realized designs validate the proposed PAs' theories/architectures.
ContributorsRoychowdhury, Debatrayee (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Aberle, James (Committee member) / Arizona State University (Publisher)
Created2024
Description
The world has seen a revolution in cellular communication with the advent of 5G (fifth-generation), which enables gigabits per second data speed with low latency, massive capacity, and increased availability. These modern wireless systems improve spectrum efficiency by employing advanced modulation techniques, but result in large peak-to-average power ratios (PAPR) of the transmitted signals that degrades the efficiency of the radio-frequency power amplifiers (PAs) in the power back-off (PBO) region. Envelope tracking (ET), which is a dynamic supply control technology to realize high efficiency PAs, is a promising approach for designing transmitters for the future. Conventional voltage regulators, such as linear regulators and switching regulators, fail to simultaneously offer high speed, high efficiency, and improved linearity. Hybrid supply modulators (HSM) that combine a linear and switching regulator emerge as promising solutions to achieve an optimized tradeoff between different design parameters. Over the years, considerable development and research efforts in industry and academia have been spent on maximizing HSM performance, and a majority of the most recently developed modulators are implemented in CMOS technology and mainly targeted for handset applications. In this dissertation, the main requirements for modern HSM designs are categorized and analyzed in detail. Next, techniques to improve HSM performance are discussed. The available device technologies for HSM and PA implementations are also delineated, and implementation challenges of an integrated ET-PA system are summarized. Finally, a Current-Mode with Dynamic Hysteresis HSM is proposed, designed, and implemented. With the proposed technique, the HSM is able to track LTE signals up to 100 MHz bandwidth. Switching at a peak frequency of 40 MHz, the design is able to track a 1 Vpp sinusoidal signal with high fidelity, has an output voltage ripple around 54 mV, and achieves a peak static and dynamic efficiency of 92.2% and 82.29%, respectively, at the maximum output. The HSM is capable of delivering a maximum output power of 425 mW and occupies a small die area of 1.6mm2. Overall, the proposed HSM promises competitive performance compared to state-of-the-art works.
ContributorsBHARDWAJ, SUMIT (Author) / Kitchen, Jennifer (Thesis advisor) / Ozev, Sule (Committee member) / Bakkaloglu, Bertan (Committee member) / Singh, Shrikant (Committee member) / Arizona State University (Publisher)
Created2024