This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students. 

Displaying 1 - 10 of 85
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Description
Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current

Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current density is of great concern affecting the reliability of the entire microelectronics systems. This paper reviews electromigration in Pb- free solders, focusing specifically on Sn0.7wt.% Cu solder joints. Effect of texture, grain orientation, and grain-boundary misorientation angle on electromigration and intermetallic compound (IMC) formation is studied through EBSD analysis performed on actual C4 bumps.
ContributorsLara, Leticia (Author) / Tasooji, Amaneh (Thesis advisor) / Lee, Kyuoh (Committee member) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Rapid processing and reduced end-of-range diffusion effects demonstrate that susceptor-assisted microwave annealing is an efficient processing alternative for electrically activating dopants and removing ion-implantation damage in ion-implanted semiconductors. Sheet resistance and Hall measurements provide evidence of electrical activation. Raman spectroscopy and ion channeling analysis monitor the extent of ion implantation

Rapid processing and reduced end-of-range diffusion effects demonstrate that susceptor-assisted microwave annealing is an efficient processing alternative for electrically activating dopants and removing ion-implantation damage in ion-implanted semiconductors. Sheet resistance and Hall measurements provide evidence of electrical activation. Raman spectroscopy and ion channeling analysis monitor the extent of ion implantation damage and recrystallization. The presence of damage and defects in ion implanted silicon, and the reduction of the defects as a result of annealing, is observed by Rutherford backscattering spectrometry, moreover, the boron implanted silicon is further investigated by cross-section transmission electron microscopy. When annealing B+ implanted silicon, the dissolution of small extended defects and growth of large extended defects result in reduced crystalline quality that hinders the electrical activation process. Compared to B+ implanted silicon, phosphorus implanted samples experience more effective activation and achieve better crystalline quality. Comparison of end-of-range dopants diffusion resulting from microwave annealing and rapid thermal annealing (RTA) is done using secondary ion mass spectroscopy. Results from microwave annealed P+ implanted samples show that almost no diffusion occurs during time periods required for complete dopant activation and silicon recrystallization. The relative contributions to heating of the sample, by a SiC susceptor, and by Si self-heating in the microwave anneal, were also investigated. At first 20s, the main contributor to the sample's temperature rise is Si self-heating by microwave absorption.
ContributorsZhao, Zhao (Author) / Alford, Terry Lynn (Thesis advisor) / Theodore, David (Committee member) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2013
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Description
This thesis work mainly examined the stability and reliability issues of amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors under bias-illumination stress. Amorphous hydrogenated silicon has been the dominating material used in thin film transistors as a channel layer. However with the advent of modern high performance display technologies,

This thesis work mainly examined the stability and reliability issues of amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors under bias-illumination stress. Amorphous hydrogenated silicon has been the dominating material used in thin film transistors as a channel layer. However with the advent of modern high performance display technologies, it is required to have devices with better current carrying capability and better reproducibility. This brings the idea of new material for channel layer of these devices. Researchers have tried poly silicon materials, organic materials and amorphous mixed oxide materials as a replacement to conventional amorphous silicon layer. Due to its low price and easy manufacturing process, amorphous mixed oxide thin film transistors have become a viable option to replace the conventional ones in order to achieve high performance display circuits. But with new materials emerging, comes the challenge of reliability and stability issues associated with it. Performance measurement under bias stress and bias-illumination stress have been reported previously. This work proposes novel post processing low temperature long time annealing in optimum ambient in order to annihilate or reduce the defects and vacancies associated with amorphous material which lead to the instability or even the failure of the devices. Thin film transistors of a-IGZO has been tested for standalone illumination stress and bias-illumination stress before and after annealing. HP 4155B semiconductor parameter analyzer has been used to stress the devices and measure the output characteristics and transfer characteristics of the devices. Extra attention has been given about the effect of forming gas annealing on a-IGZO thin film. a-IGZO thin film deposited on silicon substrate has been tested for resistivity, mobility and carrier concentration before and after annealing in various ambient. Elastic Recoil Detection has been performed on the films to measure the amount of hydrogen atoms present in the film. Moreover, the circuit parameters of the thin film transistors has been extracted to verify the physical phenomenon responsible for the instability and failure of the devices. Parameters like channel resistance, carrier mobility, power factor has been extracted and variation of these parameters has been observed before and after the stress.
ContributorsRuhul Hasin, Muhammad (Author) / Alford, Terry L. (Thesis advisor) / Krause, Stephen (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2013
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Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a

In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
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Description
III-Nitride nanostructures have been an active area of research recently due to their ability to tune their optoelectronic properties. Thus far work has been done on InGaN quantum dots, nanowires, nanopillars, amongst other structures, but this research reports the creation of a new type of InGaN nanostructure, nanorings. Hexagonal InGaN

III-Nitride nanostructures have been an active area of research recently due to their ability to tune their optoelectronic properties. Thus far work has been done on InGaN quantum dots, nanowires, nanopillars, amongst other structures, but this research reports the creation of a new type of InGaN nanostructure, nanorings. Hexagonal InGaN nanorings were formed using Metal Organic Chemical Vapor Deposition through droplet epitaxy. The nanorings were thoroughly analyzed using x-ray diffraction, photoluminescence, electron microscopy, electron diffraction, and atomic force microscopy. Nanorings with high indium incorporation were achieved with indium content up to 50% that was then controlled using the growth time, temperature, In/Ga ratio and III/N ratio. The analysis showed that the nanoring shape is able to incorporate more indium than other nanostructures, due to the relaxing mechanism involved in the formation of the nanoring. The ideal conditions were determined to be growth of 30 second droplets with a growth time of 1 minute 30 seconds at 770 C to achieve the most well developed rings with the highest indium concentration.
ContributorsZaidi, Zohair (Author) / Mahajan, Subhash (Thesis advisor) / O'Connell, Michael J (Committee member) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Zinc oxide (ZnO) has attracted much interest during last decades as a functional material. Furthermore, ZnO is a potential material for transparent conducting oxide material competing with indium tin oxide (ITO), graphene, and carbon nanotube film. It has been known as a conductive material when doped with elements such as

Zinc oxide (ZnO) has attracted much interest during last decades as a functional material. Furthermore, ZnO is a potential material for transparent conducting oxide material competing with indium tin oxide (ITO), graphene, and carbon nanotube film. It has been known as a conductive material when doped with elements such as indium, gallium and aluminum. The solubility of those dopant elements in ZnO is still debatable; but, it is necessary to find alternative conducting materials when their form is film or nanostructure for display devices. This is a consequence of the ever increasing price of indium. In addition, a new generation solar cell (nanostructured or hybrid photovoltaics) requires compatible materials which are capable of free standing on substrates without seed or buffer layers and have the ability introduce electrons or holes pathway without blocking towards electrodes. The nanostructures for solar cells using inorganic materials such as silicon (Si), titanium oxide (TiO2), and ZnO have been an interesting topic for research in solar cell community in order to overcome the limitation of efficiency for organic solar cells. This dissertation is a study of the rational solution-based synthesis of 1-dimentional ZnO nanomaterial and its solar cell applications. These results have implications in cost effective and uniform nanomanufacturing for the next generation solar cells application by controlling growth condition and by doping transition metal element in solution.
ContributorsChoi, Hyung Woo (Author) / Alford, Terry L. (Thesis advisor) / Krause, Stephen (Committee member) / Theodore, N. David (Committee member) / Arizona State University (Publisher)
Created2012
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Description
Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material,

Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.
ContributorsFallah-Adl, Ali (Author) / Tasooji, Amaneh (Thesis advisor) / Krause, Stephen (Committee member) / Alford, Terry (Committee member) / Jiang, Hanqing (Committee member) / Mahajan, Ravi (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at

Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.
ContributorsKilgore, Stephen (Author) / Adams, James (Thesis advisor) / Schroder, Dieter (Thesis advisor) / Krause, Stephen (Committee member) / Gaw, Craig (Committee member) / Arizona State University (Publisher)
Created2013
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Description
In this thesis we deal with the problem of temporal logic robustness estimation. We present a dynamic programming algorithm for the robust estimation problem of Metric Temporal Logic (MTL) formulas regarding a finite trace of time stated sequence. This algorithm not only tests if the MTL specification is satisfied by

In this thesis we deal with the problem of temporal logic robustness estimation. We present a dynamic programming algorithm for the robust estimation problem of Metric Temporal Logic (MTL) formulas regarding a finite trace of time stated sequence. This algorithm not only tests if the MTL specification is satisfied by the given input which is a finite system trajectory, but also quantifies to what extend does the sequence satisfies or violates the MTL specification. The implementation of the algorithm is the DP-TALIRO toolbox for MATLAB. Currently it is used as the temporal logic robust computing engine of S-TALIRO which is a tool for MATLAB searching for trajectories of minimal robustness in Simulink/ Stateflow. DP-TALIRO is expected to have near linear running time and constant memory requirement depending on the structure of the MTL formula. DP-TALIRO toolbox also integrates new features not supported in its ancestor FW-TALIRO such as parameter replacement, most related iteration and most related predicate. A derivative of DP-TALIRO which is DP-T-TALIRO is also addressed in this thesis which applies dynamic programming algorithm for time robustness computation. We test the running time of DP-TALIRO and compare it with FW-TALIRO. Finally, we present an application where DP-TALIRO is used as the robustness computation core of S-TALIRO for a parameter estimation problem.
ContributorsYang, Hengyi (Author) / Fainekos, Georgios (Thesis advisor) / Sarjoughian, Hessam S. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Software has a great impact on the energy efficiency of any computing system--it can manage the components of a system efficiently or inefficiently. The impact of software is amplified in the context of a wearable computing system used for activity recognition. The design space this platform opens up is immense

Software has a great impact on the energy efficiency of any computing system--it can manage the components of a system efficiently or inefficiently. The impact of software is amplified in the context of a wearable computing system used for activity recognition. The design space this platform opens up is immense and encompasses sensors, feature calculations, activity classification algorithms, sleep schedules, and transmission protocols. Design choices in each of these areas impact energy use, overall accuracy, and usefulness of the system. This thesis explores methods software can influence the trade-off between energy consumption and system accuracy. In general the more energy a system consumes the more accurate will be. We explore how finding the transitions between human activities is able to reduce the energy consumption of such systems without reducing much accuracy. We introduce the Log-likelihood Ratio Test as a method to detect transitions, and explore how choices of sensor, feature calculations, and parameters concerning time segmentation affect the accuracy of this method. We discovered an approximate 5X increase in energy efficiency could be achieved with only a 5% decrease in accuracy. We also address how a system's sleep mode, in which the processor enters a low-power state and sensors are turned off, affects a wearable computing platform that does activity recognition. We discuss the energy trade-offs in each stage of the activity recognition process. We find that careful analysis of these parameters can result in great increases in energy efficiency if small compromises in overall accuracy can be tolerated. We call this the ``Great Compromise.'' We found a 6X increase in efficiency with a 7% decrease in accuracy. We then consider how wireless transmission of data affects the overall energy efficiency of a wearable computing platform. We find that design decisions such as feature calculations and grouping size have a great impact on the energy consumption of the system because of the amount of data that is stored and transmitted. For example, storing and transmitting vector-based features such as FFT or DCT do not compress the signal and would use more energy than storing and transmitting the raw signal. The effect of grouping size on energy consumption depends on the feature. For scalar features energy consumption is proportional in the inverse of grouping size, so it's reduced as grouping size goes up. For features that depend on the grouping size, such as FFT, energy increases with the logarithm of grouping size, so energy consumption increases slowly as grouping size increases. We find that compressing data through activity classification and transition detection significantly reduces energy consumption and that the energy consumed for the classification overhead is negligible compared to the energy savings from data compression. We provide mathematical models of energy usage and data generation, and test our ideas using a mobile computing platform, the Texas Instruments Chronos watch.
ContributorsBoyd, Jeffrey Michael (Author) / Sundaram, Hari (Thesis advisor) / Li, Baoxin (Thesis advisor) / Shrivastava, Aviral (Committee member) / Turaga, Pavan (Committee member) / Arizona State University (Publisher)
Created2014