Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
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- Creators: Bakkaloglu, Bertan
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
ContributorsSuh, Jounghyuk (Author) / Bakkaloglu, Bertan (Thesis advisor) / Cao, Yu (Committee member) / Ozev, Sule (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Several state of the art, monitoring and control systems, such as DC motor
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
ContributorsThirunakkarasu, Shankar (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kozicki, Michael (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2014
Description
Power supply management is important for MEMS (Micro-Electro-Mechanical-Systems) bio-sensing and chemical sensing applications. The dissertation focuses on discussion of accessibility to different power sources and supply tuning in sensing applications. First, the dissertation presents a high efficiency DC-DC converter for a miniaturized Microbial Fuel Cell (MFC). The miniaturized MFC produces up to approximately 10µW with an output voltage of 0.4-0.7V. Such a low voltage, which is also load dependent, prevents the MFC to directly drive low power electronics. A PFM (Pulse Frequency Modulation) type DC-DC converter in DCM (Discontinuous Conduction Mode) is developed to address the challenges and provides a load independent output voltage with high conversion efficiency. The DC-DC converter, implemented in UMC 0.18µm technology, has been thoroughly characterized, coupled with the MFC. At 0.9V output, the converter has a peak efficiency of 85% with 9µW load, highest efficiency over prior publication. Energy could be harvested wirelessly and often has profound impacts on system performance. The dissertation reports a side-by-side comparison of two wireless and passive sensing systems: inductive and electromagnetic (EM) couplings for an application of in-situ and real-time monitoring of wafer cleanliness in semiconductor facilities. The wireless system, containing the MEMS sensor works with battery-free operations. Two wireless systems based on inductive and EM couplings have been implemented. The working distance of the inductive coupling system is limited by signal-to-noise-ratio (SNR) while that of the EM coupling is limited by the coupled power. The implemented on-wafer transponders achieve a working distance of 6 cm and 25 cm with a concentration resolution of less than 2% (4 ppb for a 200 ppb solution) for inductive and EM couplings, respectively. Finally, the supply tuning is presented in bio-sensing application to mitigate temperature sensitivity. The FBAR (film bulk acoustic resonator) based oscillator is an attractive method in label-free sensing application. Molecular interactions on FBAR surface induce mass change, which results in resonant frequency shift of FBAR. While FBAR has a high-Q to be sensitive to the molecular interactions, FBAR has finite temperature sensitivity. A temperature compensation technique is presented that improves the temperature coefficient of a 1.625 GHz FBAR-based oscillator from -118 ppm/K to less than 1 ppm/K by tuning the supply voltage of the oscillator. The tuning technique adds no additional component and has a large frequency tunability of -4305 ppm/V.
ContributorsZhang, Xu (Author) / Chae, Junseok (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Kozicki, Michael (Committee member) / Phillips, Stephen (Committee member) / Arizona State University (Publisher)
Created2012