Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
Displaying 1 - 10 of 131
Description
When people pick up the phone to call a telephone quitline, they are taking an important step towards changing their smoking behavior. The current study investigated the role of a critical cognition in the cessation process--self-efficacy. Self-efficacy is thought to be influential in behavior change processes including those involved in the challenging process of stopping tobacco use. By applying basic principles of self-efficacy theory to smokers utilizing a telephone quitline, this study advanced our understanding of the nature of self-efficacy in a "real-world" cessation setting. Participants received between one and four intervention calls aimed at supporting them through their quit attempt. Concurrent with the initiation of this study, three items (confidence, stress, and urges) were added to the standard telephone protocol and assessed at each call. Two principal sets of hypotheses were tested using a combination of ANCOVAs and multiple regression analyses. The first set of hypotheses explored how self-efficacy and changes in self-efficacy within individuals were associated with cessation outcomes. Most research has found a positive linear relation between self-efficacy and quit outcomes, but this study tested the possibility that excessively high self-efficacy may actually reflect an overconfidence bias, and in some cases be negatively related to cessation outcomes. The second set of hypotheses addressed several smoking-related factors expected to affect self-efficacy. As predicted, higher baseline self-efficacy and increases in self-efficacy were associated with higher rates of quitting. However, contrary to predictions, there was no evidence that overconfidence led to diminished cessation success. Finally, as predicted, shorter duration of quit attempts, shorter time to relapse, and stronger urges all were associated with lower self-efficacy. In conclusion, understanding how self-efficacy and changes in self-efficacy affect and are affected by cessation outcomes is useful for informing both future research and current quitline intervention procedures.
ContributorsGoesling, Jenna (Author) / Barrera, Manuel (Thesis advisor) / Shiota, Lani (Committee member) / Enders, Craig (Committee member) / Presson, Clark (Committee member) / Arizona State University (Publisher)
Created2011
Description
Residue number systems have gained significant importance in the field of high-speed digital signal processing due to their carry-free nature and speed-up provided by parallelism. The critical aspect in the application of RNS is the selection of the moduli set and the design of the conversion units. There have been several RNS moduli sets proposed for the implementation of digital filters. However, some are unbalanced and some do not provide the required dynamic range. This thesis addresses the drawbacks of existing RNS moduli sets and proposes a new moduli set for efficient implementation of FIR filters. An efficient VLSI implementation model has been derived for the design of a reverse converter from RNS to the conventional two's complement representation. This model facilitates the realization of a reverse converter for better performance with less hardware complexity when compared with the reverse converter designs of the existing balanced 4-moduli sets. Experimental results comparing multiply and accumulate units using RNS that are implemented using the proposed four-moduli set with the state-of-the-art balanced four-moduli sets, show large improvements in area (46%) and power (43%) reduction for various dynamic ranges. RNS FIR filters using the proposed moduli-set and existing balanced 4-moduli set are implemented in RTL and compared for chip area and power and observed 20% improvements. This thesis also presents threshold logic implementation of the reverse converter.
ContributorsChalivendra, Gayathri (Author) / Vrudhula, Sarma (Thesis advisor) / Shrivastava, Aviral (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
This research describes software based remote attestation schemes for obtaining the integrity of an executing user application and the Operating System (OS) text section of an untrusted client platform. A trusted external entity issues a challenge to the client platform. The challenge is executable code which the client must execute, and the code generates results which are sent to the external entity. These results provide the external entity an assurance as to whether the client application and the OS are in pristine condition. This work also presents a technique where it can be verified that the application which was attested, did not get replaced by a different application after completion of the attestation. The implementation of these three techniques was achieved entirely in software and is backward compatible with legacy machines on the Intel x86 architecture. This research also presents two approaches to incorporating software based "root of trust" using Virtual Machine Monitors (VMMs). The first approach determines the integrity of an executing Guest OS from the Host OS using Linux Kernel-based Virtual Machine (KVM) and qemu emulation software. The second approach implements a small VMM called MIvmm that can be utilized as a trusted codebase to build security applications such as those implemented in this research. MIvmm was conceptualized and implemented without using any existing codebase; its minimal size allows it to be trustworthy. Both the VMM approaches leverage processor support for virtualization in the Intel x86 architecture.
ContributorsSrinivasan, Raghunathan (Author) / Dasgupta, Partha (Thesis advisor) / Colbourn, Charles (Committee member) / Shrivastava, Aviral (Committee member) / Huang, Dijiang (Committee member) / Dewan, Prashant (Committee member) / Arizona State University (Publisher)
Created2011
Description
Fibromyalgia (FM) is a chronic musculoskeletal disorder characterized by widespread pain, fatigue, and a variety of other comorbid physiological and psychological characteristics, including a deficit of positive affect. Recently, the focus of research on the pathophysiology of FM has considered the role of a number of genomic variants. In the current manuscript, case-control analyses did not support the hypothesis that FM patients would differ from other chronic pain groups in catechol-O-methyltransferase (COMT) and mu-opioid receptor (OPRM1) genotype. However, evidence is provided in support of the hypothesis that functional single nucleotide polymorphisms on the COMT and OPRM1 genes would be associated with risk and resilience, respectively, in a dual processing model of pain-related positive affective regulation in FM. Forty-six female patients with a physician-confirmed diagnosis of FM completed an electronic diary that included once-daily assessments of positive affect and soft tissue pain. Multilevel modeling yielded a significant gene X environment interaction, such that individuals with met/met genotype on COMT experienced a greater decline in positive affect as daily pain increased than did either val/met or val/val individuals. A gene X environment interaction for OPRM1 also emerged, indicating that individuals with at least one asp allele were more resilient to elevations in daily pain than those homozygous for the asn allele. In sum, the findings offer researchers ample reason to further investigate the contribution of the catecholamine and opioid systems, and their associated genomic variants, to the still poorly understood experience of FM.
ContributorsFinan, Patrick Hamilton (Author) / Zautra, Alex (Thesis advisor) / Davis, Mary (Committee member) / Lemery-Chalfant, Kathryn (Committee member) / Presson, Clark (Committee member) / Arizona State University (Publisher)
Created2011
Description
Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal techniques. Simulation based microprocessor validation involves running millions of cycles using random or pseudo random tests and allows verification of the register transfer level (RTL) model against an architectural model, i.e., that the processor executes instructions as required. The validation effort involves model checking to a high level description or simulation of the design against the RTL implementation. Formal techniques exhaustively analyze parts of the design but, do not verify RTL against the architecture specification. The focus of this work is to implement a fully automated validation environment for a MIPS based radiation hardened microprocessor using simulation based approaches. The basic framework uses the classical validation approach in which the design to be validated is described in a Hardware Definition Language (HDL) such as VHDL or Verilog. To implement a simulation based approach a number of random or pseudo random tests are generated. The output of the HDL based design is compared against the one obtained from a "perfect" model implementing similar functionality, a mismatch in the results would thus indicate a bug in the HDL based design. Effort is made to design the environment in such a manner that it can support validation during different stages of the design cycle. The validation environment includes appropriate changes so as to support architecture changes which are introduced because of radiation hardening. The manner in which the validation environment is build is highly dependent on the specifications of the perfect model used for comparisons. This work implements the validation environment for two MIPS simulators as the reference model. Two bugs have been discovered in the RTL model, using simulation based approaches through the validation environment.
ContributorsSharma, Abhishek (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2011
Description
The use of synthetic cathinones or "bath salts" has risen dramatically in recent years with one of the most popular being Methylendioxypyrovalerone (MDPV). Following the temporary legislative ban on the sale and distribution of this compound , a multitude of other cathinone derivatives have been synthesized. The current study seeks to compare the abuse potential of MDPV with one of the emergent synthetic cathinones 4-methylethcathinone (4-MEC), based on their respective ability to lower current thresholds in an intracranial self-stimulation (ICSS) paradigm. Following acute administration (0.1, 0.5, 1 and 2 mg/kg i.p.) MDPV was found to significantly lower ICSS thresholds at all doses tested (F4,35=11.549, p<0.001). However, following acute administration (0.3,1,3,10,30 mg/kg i.p) 4-MEC produced no significant ICSS threshold depression (F5,135= 0.622, p = 0.684). Together these findings suggest that while MDPV may possess significant abuse potential, other synthetic cathinones such as 4-MEC may have a drastically reduced potential for abuse.
ContributorsWegner, Scott Andrew (Author) / Olive, M. Foster (Thesis director) / Presson, Clark (Committee member) / Sanabria, Federico (Committee member) / Barrett, The Honors College (Contributor) / Department of Chemistry and Biochemistry (Contributor) / Department of Psychology (Contributor)
Created2013-05
Description
This study looked at the gender roles of individuals in the LGBT community, who hold gender-inverting and gender-conforming queer identities. The specific identities looked at were twinks (gender-inverted) and bears (gender-conforming) for men, and lipsticks (gender-conforming) and butches (gender-inverting) for women. The hypothesis was that individuals with gender-inverting identities would react effectively to a masculine gender role selecting prime, as well as a feminine gender role selecting prime.
ContributorsBlankenship, Benjamin Tyrus (Author) / Nagoshi, Craig (Thesis director) / Presson, Clark (Committee member) / Grzanka, Patrick (Committee member) / Barrett, The Honors College (Contributor) / Department of Psychology (Contributor)
Created2013-05
Description
This research is focused on two separate but related topics. The first uses an electroencephalographic (EEG) brain-computer interface (BCI) to explore the phenomenon of motor learning transfer. The second takes a closer look at the EEG-BCI itself and tests an alternate way of mapping EEG signals into machine commands. We test whether motor learning transfer is more related to use of shared neural structures between imagery and motor execution or to more generalized cognitive factors. Using an EEG-BCI, we train one group of participants to control the movements of a cursor using embodied motor imagery. A second group is trained to control the cursor using abstract motor imagery. A third control group practices moving the cursor using an arm and finger on a touch screen. We hypothesized that if motor learning transfer is related to the use of shared neural structures then the embodied motor imagery group would show more learning transfer than the abstract imaging group. If, on the other hand, motor learning transfer results from more general cognitive processes, then the abstract motor imagery group should also demonstrate motor learning transfer to the manual performance of the same task. Our findings support that motor learning transfer is due to the use of shared neural structures between imaging and motor execution of a task. The abstract group showed no motor learning transfer despite being better at EEG-BCI control than the embodied group. The fact that more participants were able to learn EEG-BCI control using abstract imagery suggests that abstract imagery may be more suitable for EEG-BCIs for some disabilities, while embodied imagery may be more suitable for others. In Part 2, EEG data collected in the above experiment was used to train an artificial neural network (ANN) to map EEG signals to machine commands. We found that our open-source ANN using spectrograms generated from SFFTs is fundamentally different and in some ways superior to Emotiv's proprietary method. Our use of novel combinations of existing technologies along with abstract and embodied imagery facilitates adaptive customization of EEG-BCI control to meet needs of individual users.
Contributorsda Silva, Flavio J. K (Author) / Mcbeath, Michael K (Thesis advisor) / Helms Tillery, Stephen (Committee member) / Presson, Clark (Committee member) / Sugar, Thomas (Committee member) / Arizona State University (Publisher)
Created2013
Description
In this thesis we deal with the problem of temporal logic robustness estimation. We present a dynamic programming algorithm for the robust estimation problem of Metric Temporal Logic (MTL) formulas regarding a finite trace of time stated sequence. This algorithm not only tests if the MTL specification is satisfied by the given input which is a finite system trajectory, but also quantifies to what extend does the sequence satisfies or violates the MTL specification. The implementation of the algorithm is the DP-TALIRO toolbox for MATLAB. Currently it is used as the temporal logic robust computing engine of S-TALIRO which is a tool for MATLAB searching for trajectories of minimal robustness in Simulink/ Stateflow. DP-TALIRO is expected to have near linear running time and constant memory requirement depending on the structure of the MTL formula. DP-TALIRO toolbox also integrates new features not supported in its ancestor FW-TALIRO such as parameter replacement, most related iteration and most related predicate. A derivative of DP-TALIRO which is DP-T-TALIRO is also addressed in this thesis which applies dynamic programming algorithm for time robustness computation. We test the running time of DP-TALIRO and compare it with FW-TALIRO. Finally, we present an application where DP-TALIRO is used as the robustness computation core of S-TALIRO for a parameter estimation problem.
ContributorsYang, Hengyi (Author) / Fainekos, Georgios (Thesis advisor) / Sarjoughian, Hessam S. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2013
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013