Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
Displaying 41 - 50 of 98
Description
Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.
Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.
ContributorsHegde, Ashwath (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
VCO as a ubiquitous circuit in many systems is highly demanding for the phase noises. Lowering the noise migrated from the power supply has been the trending topics for many years. Considering the Ring Oscillator(RO) based VCO is more sensitive to the supply noise, it is more significant to find out a useful technique to reduce the supply noise. Among the conventional supply noise reduction techniques such as filtering, channel length adjusting for the transistors, and the current noise mutual canceling, the new feature of the 28nm UTBB-FD-SOI process launched by the ST semiconductor offered a new method to reduce the noise, which is realized by allowing the circuit designer to dynamically control the threshold voltage. In this thesis, a new structure of the linear coarse-fine VCO with 1V supply voltage is designed for the ring typed VCO. The structure is also designed to be flexible to tune the frequency coverage by the fine and coarse tunable on-board resistors. The thesis has given the model of the phase noise reduction method. The model has also been proved to be meaningful with the newly designed VCO circuit. For instances, given 1μV/√Hz white noise coupled on the supply, the 3GHz VCO can have a more than 7dBc/Hz phase noise lowering at the 10MHz frequency offset.
ContributorsTang, Miao (Author) / Barnaby, Hugh (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Mikkola, Esko (Committee member) / Arizona State University (Publisher)
Created2018
Description
Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application.
In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency.
The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.
In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency.
The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.
ContributorsLim, Chai Yong (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018
Description
The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel.
Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.
ContributorsBensalem, Brahim (Author) / Aberle, James T. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Tirkas, Panayiotis A. (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
In this dissertation a new wideband circular HIS is proposed. The circular periodicity made it possible to illuminate the surface with a cylindrical TEMz wave and; a novel technique is utilized to make it wideband. Two models are developed to analyze the
reflection characteristics of the proposed HIS.
The circularly symmetric high impedance surface is used as a ground plane for the design of a low-profile loop and spiral radiating elements. It is shown that a HIS with circular periodicity provides a wider operational bandwidth for curvilinear radiating elements such, such as loops and spirals, compared to canonical rectangular HISs.
It is also observed that, with the aid of a circular HIS ground plane the gain of a loop and a spiral increases compared to when a perfect magnetic conductor (PMC) or rectangular HIS is used as a ground plane. The circular HIS was fabricated and the loop and spiral elements were placed individually in close proximity to it.
Also, due to the growing demand for low-radar signature (RCS) antennas for advanced airborne vehicles, curved and flexible HIS ground planes, which meet both the aerodynamic and low RCS requirements, have recently become popular candidates within the antenna and microwave technology. This encouraged us, to propose a spherical HIS where a 2-D curvature is introduced to the previously designed flat HIS.
The major problem associated with spherical HIS is the impact of the curvature on its reflection properties. After characterization of the flat circular HIS, which is addressed in the first part of this dissertation, a spherical curvature is introduced to the flat circular HIS and its impact on the reflection properties was examined when it was illuminated with the same cylindrical TEMz wave. The same technique, as for the flat HIS ground plane, is utilized to make the spherical HIS wideband. A loop and spiral element were placed in the vicinity of the curved HIS and their performanceswere investigated. The HISs were also fabricated and measurements were conducted to verify the simulations. An excellent agreement was observed.
reflection characteristics of the proposed HIS.
The circularly symmetric high impedance surface is used as a ground plane for the design of a low-profile loop and spiral radiating elements. It is shown that a HIS with circular periodicity provides a wider operational bandwidth for curvilinear radiating elements such, such as loops and spirals, compared to canonical rectangular HISs.
It is also observed that, with the aid of a circular HIS ground plane the gain of a loop and a spiral increases compared to when a perfect magnetic conductor (PMC) or rectangular HIS is used as a ground plane. The circular HIS was fabricated and the loop and spiral elements were placed individually in close proximity to it.
Also, due to the growing demand for low-radar signature (RCS) antennas for advanced airborne vehicles, curved and flexible HIS ground planes, which meet both the aerodynamic and low RCS requirements, have recently become popular candidates within the antenna and microwave technology. This encouraged us, to propose a spherical HIS where a 2-D curvature is introduced to the previously designed flat HIS.
The major problem associated with spherical HIS is the impact of the curvature on its reflection properties. After characterization of the flat circular HIS, which is addressed in the first part of this dissertation, a spherical curvature is introduced to the flat circular HIS and its impact on the reflection properties was examined when it was illuminated with the same cylindrical TEMz wave. The same technique, as for the flat HIS ground plane, is utilized to make the spherical HIS wideband. A loop and spiral element were placed in the vicinity of the curved HIS and their performanceswere investigated. The HISs were also fabricated and measurements were conducted to verify the simulations. An excellent agreement was observed.
ContributorsAmiri, Mikal Askarian (Author) / Balanis, Constantine A (Thesis advisor) / Aberle, James T (Committee member) / Bakkaloglu, Bertan (Committee member) / Trichopoulos, Georgios C (Committee member) / Arizona State University (Publisher)
Created2018
Description
This work is concerned with the use of shielded loop antennas to measure
permittivity as a low-cost alternative to expensive probe-based systems for biological
tissues and surrogates. Beginning with the development of a model for simulation, the
shielded loop was characterized. Following the simulations, the shielded loop was tested
in free space and while holding a cup of water. The results were then compared. Because
the physical measurements and the simulation results did not line up, simulation results
were forgone. The shielded loop antenna was then used to measure a set of NaCl saline
solutions with varying molarities. This measurement was used as a calibration set, and
the results were analyzed. By taking the peak magnitude of the input impedance of each
solution, a trend was created for the molarities. Following this measurement and analysis,
a set of unknown solutions was tested. Based on the measurements and the empirical
trends from the calibration set of measurements, the molarities of the valid unknown
solutions were estimated. It is shown that using the known molarities, permittivity can
also be calculated. Using the estimated molarities of the unknown solutions, the
permittivity of each solution was calculated. The maximum error for the estimation was
1.07% from the actual data.
permittivity as a low-cost alternative to expensive probe-based systems for biological
tissues and surrogates. Beginning with the development of a model for simulation, the
shielded loop was characterized. Following the simulations, the shielded loop was tested
in free space and while holding a cup of water. The results were then compared. Because
the physical measurements and the simulation results did not line up, simulation results
were forgone. The shielded loop antenna was then used to measure a set of NaCl saline
solutions with varying molarities. This measurement was used as a calibration set, and
the results were analyzed. By taking the peak magnitude of the input impedance of each
solution, a trend was created for the molarities. Following this measurement and analysis,
a set of unknown solutions was tested. Based on the measurements and the empirical
trends from the calibration set of measurements, the molarities of the valid unknown
solutions were estimated. It is shown that using the known molarities, permittivity can
also be calculated. Using the estimated molarities of the unknown solutions, the
permittivity of each solution was calculated. The maximum error for the estimation was
1.07% from the actual data.
ContributorsYiin, Nathan (Author) / Aberle, James T., 1961- (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
As integrated technologies are scaling down, there is an increasing trend in the
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
process,voltage and temperature (PVT) variations of highly integrated RF systems.
Accounting for these variations during the design phase requires tremendous amount
of time for prediction of RF performance and optimizing it accordingly. Thus, there
is an increasing gap between the need to relax the RF performance requirements at
the design phase for rapid development and the need to provide high performance
and low cost RF circuits that function with PVT variations. No matter how care-
fully designed, RF integrated circuits (ICs) manufactured with advanced technology
nodes necessitate lengthy post-production calibration and test cycles with expensive
RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast
measurement of performance parameters during both post-production and in-eld op-
eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip
measurement of RF performance parameters. In this dissertation, three aspects of
automated test and calibration, including DFT mathematical model, BIST hardware
and built-in calibration are covered for RF front-end blocks.
First, the theoretical foundation of a post-production test of RF integrated phased
array antennas is proposed by developing the mathematical model to measure gain
and phase mismatches between antenna elements without any electrical contact. The
proposed technique is fast, cost-efficient and uses near-field measurement of radiated
power from antennas hence, it requires single test setup, it has easy implementation
and it is short in time which makes it viable for industrialized high volume integrated
IC production test.
Second, a BIST model intended for the characterization of I/Q offset, gain and
phase mismatch of IQ transmitters without relying on external equipment is intro-
duced. The proposed BIST method is based on on-chip amplitude measurement as
in prior works however,here the variations in the BIST circuit do not affect the target
parameter estimation accuracy since measurements are designed to be relative. The
BIST circuit is implemented in 130nm technology and can be used for post-production
and in-field calibration.
Third, a programmable low noise amplifier (LNA) is proposed which is adaptable
to different application scenarios depending on the specification requirements. Its
performance is optimized with regards to required specifications e.g. distance, power
consumption, BER, data rate, etc.The statistical modeling is used to capture the
correlations among measured performance parameters and calibration modes for fast
adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by
embedding built-in tuning knobs in LNA design in 130nm technology. The tuning
knobs are carefully designed to provide independent combinations of important per-
formance parameters such as gain and linearity. Minimum number of switches are
used to provide the desired tuning range without a need for an external analog input.
ContributorsShafiee, Maryam (Author) / Ozev, Sule (Thesis advisor) / Diaz, Rodolfo (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2018
Description
The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.
ContributorsRuhul Hasin, Muhammad (Author) / Kitchen, Jennifer (Thesis advisor) / Aberle, James T., 1961- (Committee member) / Bakkaloglu, Bertan (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2018
Description
This work covers the design and implementation of a Parallel Doherty RF Power Amplifier in a GaN HEMT process for medium power macro-cell (16W) base station applications. This work improves the key parameters of a Doherty Power Amplifier including the peak and back-off efficiency, operational instantaneous bandwidth and output power by proposing a Parallel Doherty amplifier architecture.
As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.
The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.
As there is a progression in the wireless communication systems from the first generation to the future 5G systems, there is ever increasing demand for higher data rates which means signals with higher peak-to-average power ratios (PAPR). The present modulation schemes require PAPRs close to 8-10dB. So, there is an urgent need to develop energy efficient power amplifiers that can transmit these high data rate signals.
The Doherty Power Amplifier (DPA) is the most common PA architecture in the cellular infrastructure, as it achieves reasonably high back-off power levels with good efficiency. This work advances the DPA architecture by proposing a Parallel Doherty Power Amplifier to broaden the PAs instantaneous bandwidth, designed with frequency range of operation for 2.45 – 2.70 GHz to support WiMAX applications and future broadband signals.
ContributorsBHARDWAJ, SUMIT (Author) / Kitchen, Jennifer (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2018
Description
Fraud is defined as the utilization of deception for illegal gain by hiding the true nature of the activity. While organizations lose around $3.7 trillion in revenue due to financial crimes and fraud worldwide, they can affect all levels of society significantly. In this dissertation, I focus on credit card fraud in online transactions. Every online transaction comes with a fraud risk and it is the merchant's liability to detect and stop fraudulent transactions. Merchants utilize various mechanisms to prevent and manage fraud such as automated fraud detection systems and manual transaction reviews by expert fraud analysts. Many proposed solutions mostly focus on fraud detection accuracy and ignore financial considerations. Also, the highly effective manual review process is overlooked. First, I propose Profit Optimizing Neural Risk Manager (PONRM), a selective classifier that (a) constitutes optimal collaboration between machine learning models and human expertise under industrial constraints, (b) is cost and profit sensitive. I suggest directions on how to characterize fraudulent behavior and assess the risk of a transaction. I show that my framework outperforms cost-sensitive and cost-insensitive baselines on three real-world merchant datasets. While PONRM is able to work with many supervised learners and obtain convincing results, utilizing probability outputs directly from the trained model itself can pose problems, especially in deep learning as softmax output is not a true uncertainty measure. This phenomenon, and the wide and rapid adoption of deep learning by practitioners brought unintended consequences in many situations such as in the infamous case of Google Photos' racist image recognition algorithm; thus, necessitated the utilization of the quantified uncertainty for each prediction. There have been recent efforts towards quantifying uncertainty in conventional deep learning methods (e.g., dropout as Bayesian approximation); however, their optimal use in decision making is often overlooked and understudied. Thus, I present a mixed-integer programming framework for selective classification called MIPSC, that investigates and combines model uncertainty and predictive mean to identify optimal classification and rejection regions. I also extend this framework to cost-sensitive settings (MIPCSC) and focus on the critical real-world problem, online fraud management and show that my approach outperforms industry standard methods significantly for online fraud management in real-world settings.
ContributorsYildirim, Mehmet Yigit (Author) / Davulcu, Hasan (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Huang, Dijiang (Committee member) / Hsiao, Ihan (Committee member) / Arizona State University (Publisher)
Created2019