Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
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- Creators: Ganesan, Kousik
- Creators: Korobeinikov, Yuri
Description
The characterization of interface properties in molten slag is crucial for understanding the interface phenomenon and the reactions between slag and metal. This study focuses on examining the influence of Cr2O3, an important surface active oxide, on the wettability and surface tension of slag. Industrial Electric Arc Furnace (EAF) slag with two different Cr2O3 contents (1 wt% and 3 wt%) was investigated using the sessile drop measurement technique at a high temperature of 1650°C. For the preparation of 3 wt% Cr2O3-doped slags, the following crucibles were used: Al2O3, Mo, and MgO. The behavior of crucibles, the dissolution process as well as its effect on the slag thermophysical properties were studied. For the evaluation of surface tension, Mo and MgO substrates were used. The contact angle was measured using the sessile drop method, and the surface tension was calculated using the Young-Laplace-based software. The interaction and wettability behavior between the slag and different substrates was studied. The effects of Cr2O3 content, in correlation with Al2O3, Mo, and MgO, as well as temperature, on the surface tension, and phase formation were analyzed using FactSage 8.2. The results indicate an increase in the formation of solid phases with Al2O3 and Mo dissolution into the slag. The composition of the MoO3 is confirmed with the XRF and EDS analysis. Furthermore, an increase in the formation of the spinel phase was observed with the addition of chromium, which is confirmed via XRD. The increase in the CaCrMo-oxide-based spinel led to a decrease in the surface tension of the slag. The surface tension of the slag pre-melted in a Mo, decreases as the Cr2O3 content increases. The effects of the amounts of Cr2O3 in correlation with Al2O3, MgO, and MoO3 on the slag foaming index were determined using the existing models in the literature.
ContributorsMeena, Neha (Author) / Seetharaman, Sridhar (Thesis advisor) / Alford, Terry (Committee member) / Korobeinikov, Yuri (Committee member) / Arizona State University (Publisher)
Created2023
Description
This work demonstrates a capable reverse pulse deposition methodology to influence gap fill behavior inside microvia along with a uniform deposit in the fine line patterned regions for substrate packaging applications. Interconnect circuitry in IC substrate packages comprises of stacked microvia that varies in depth from 20µm to 100µm with an aspect ratio of 0.5 to 1.5 and fine line patterns defined by photolithography. Photolithography defined pattern regions incorporate a wide variety of feature sizes including large circular pad structures with diameter of 20µm - 200µm, fine traces with varying widths of 3µm - 30µm and additional planar regions to define a IC substrate package. Electrodeposition of copper is performed to establish the desired circuit. Electrodeposition of copper in IC substrate applications holds certain unique challenges in that they require a low cost manufacturing process that enables a void-free gap fill inside the microvia along with uniform deposition of copper on exposed patterned regions. Deposition time scales to establish the desired metal thickness for such packages could range from several minutes to few hours. This work showcases a reverse pulse electrodeposition methodology that achieves void-free gap fill inside the microvia and uniform plating in FLS (Fine Lines and Spaces) regions with significantly higher deposition rates than traditional approaches. In order to achieve this capability, systematic experimental and simulation studies were performed. A strong correlation of independent parameters that govern the electrodeposition process such as bath temperature, reverse pulse plating parameters and the ratio of electrolyte concentrations is shown to the deposition kinetics and deposition uniformity in fine patterned regions and gap fill rate inside the microvia. Additionally, insight into the physics of via fill process is presented with secondary and tertiary current simulation efforts. Such efforts lead to show “smart” control of deposition rate at the top and bottom of via to avoid void formation. Finally, a parametric effect on grain size and the ensuing copper metallurgical characteristics of bulk copper is also shown to enable high reliability substrate packages for the IC packaging industry.
ContributorsGanesan, Kousik (Author) / Tasooji, Amaneh (Thesis advisor) / Manepalli, Rahul (Committee member) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2018