Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
Displaying 1 - 10 of 107
Description
The overall goal of this research project was to assess the feasibility of investigating the effects of microgravity on mineralization systems in unit gravity environments. If possible to perform these studies in unit gravity earth environments, such as earth, such systems can offer markedly less costly and more concerted research efforts to study these vitally important systems. Expected outcomes from easily accessible test environments and more tractable studies include the development of more advanced and adaptive material systems, including biological systems, particularly as humans ponder human exploration in deep space. The specific focus of the research was the design and development of a prototypical experimental test system that could preliminarily meet the challenging design specifications required of such test systems. Guided by a more unified theoretical foundation and building upon concept design and development heuristics, assessment of the feasibility of two experimental test systems was explored. Test System I was a rotating wall reactor experimental system that closely followed the specifications of a similar test system, Synthecon, designed by NASA contractors and thus closely mimicked microgravity conditions of the space shuttle and station. The latter includes terminal velocity conditions experienced by both innate material systems, as well as, biological systems, including living tissue and humans but has the ability to extend to include those material test systems associated with mineralization processes. Test System II is comprised of a unique vertical column design that offered more easily controlled fluid mechanical test conditions over a much wider flow regime that was necessary to achieving terminal velocities under free convection-less conditions that are important in mineralization processes. Preliminary results indicate that Test System II offers distinct advantages in studying microgravity effects in test systems operating in unit gravity environments and particularly when investigating mineralization and related processes. Verification of the Test System II was performed on validating microgravity effects on calcite mineralization processes reported earlier others. There studies were conducted on calcite mineralization in fixed-wing, reduced gravity aircraft, known as the `vomit comet' where reduced gravity conditions are include for very short (~20second) time periods. Preliminary results indicate that test systems, such as test system II, can be devised to assess microgravity conditions in unit gravity environments, such as earth. Furthermore, the preliminary data obtained on calcite formation suggest that strictly physicochemical mechanisms may be the dominant factors that control adaptation in materials processes, a theory first proposed by Liu et al. Thus the result of this study may also help shine a light on the problem of early osteoporosis in astronauts and long term interest in deep space exploration.
ContributorsSeyedmadani, Kimia (Author) / Pizziconi, Vincent (Thesis advisor) / Towe, Bruce (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2013
Description
As crystalline silicon solar cells continue to get thinner, the recombination of carriers at the surfaces of the cell plays an ever-important role in controlling the cell efficiency. One tool to minimize surface recombination is field effect passivation from the charges present in the thin films applied on the cell surfaces. The focus of this work is to understand the properties of charges present in the SiNx films and then to develop a mechanism to manipulate the polarity of charges to either negative or positive based on the end-application. Specific silicon-nitrogen dangling bonds (·Si-N), known as K center defects, are the primary charge trapping defects present in the SiNx films. A custom built corona charging tool was used to externally inject positive or negative charges in the SiNx film. Detailed Capacitance-Voltage (C-V) measurements taken on corona charged SiNx samples confirmed the presence of a net positive or negative charge density, as high as +/- 8 x 1012 cm-2, present in the SiNx film. High-energy (~ 4.9 eV) UV radiation was used to control and neutralize the charges in the SiNx films. Electron-Spin-Resonance (ESR) technique was used to detect and quantify the density of neutral K0 defects that are paramagnetically active. The density of the neutral K0 defects increased after UV treatment and decreased after high temperature annealing and charging treatments. Etch-back C-V measurements on SiNx films showed that the K centers are spread throughout the bulk of the SiNx film and not just near the SiNx-Si interface. It was also shown that the negative injected charges in the SiNx film were stable and present even after 1 year under indoor room-temperature conditions. Lastly, a stack of SiO2/SiNx dielectric layers applicable to standard commercial solar cells was developed using a low temperature (< 400 °C) PECVD process. Excellent surface passivation on FZ and CZ Si substrates for both n- and p-type samples was achieved by manipulating and controlling the charge in SiNx films.
ContributorsSharma, Vivek (Author) / Bowden, Stuart (Thesis advisor) / Schroder, Dieter (Committee member) / Honsberg, Christiana (Committee member) / Roedel, Ronald (Committee member) / Alford, Terry (Committee member) / Arizona State University (Publisher)
Created2013
Description
Microwave dielectrics are widely used to make resonators and filters in telecommunication systems. The production of thin films with high dielectric constant and low loss could potentially enable a marked reduction in the size of devices and systems. However, studies of these materials in thin film form are very sparse. In this research, experiments were carried out on practical high-performance dielectrics including ZrTiO4-ZnNb2O6 (ZTZN) and Ba(Co,Zn)1/3Nb2/3O3 (BCZN) with high dielectric constant and low loss tangent. Thin films were deposited by laser ablation on various substrates, with a systematical study of growth conditions like substrate temperature, oxygen pressure and annealing to optimize the film quality, and the compositional, microstructural, optical and electric properties were characterized. The deposited ZTZN films were randomly oriented polycrystalline on Si substrate and textured on MgO substrate with a tetragonal lattice change at elevated temperature. The BCZN films deposited on MgO substrate showed superior film quality relative to that on other substrates, which grow epitaxially with an orientation of (001) // MgO (001) and (100) // MgO (100) when substrate temperature was above 500 oC. In-situ annealing at growth temperature in 200 mTorr oxygen pressure was found to enhance the quality of the films, reducing the peak width of the X-ray Diffraction (XRD) rocking curve to 0.53o and the χmin of channeling Rutherford Backscattering Spectrometry (RBS) to 8.8% when grown at 800oC. Atomic Force Microscopy (AFM) was used to study the topography and found a monotonic decrease in the surface roughness when the growth temperature increased. Optical absorption and transmission measurements were used to determine the energy bandgap and the refractive index respectively. A low-frequency dielectric constant of 34 was measured using a planar interdigital measurement structure. The resistivity of the film is ~3×1010 ohm·cm at room temperature and has an activation energy of thermal activated current of 0.66 eV.
ContributorsLi, You (Author) / Newman, Nathan (Thesis advisor) / Alford, Terry (Committee member) / Singh, Rakesh (Committee member) / Arizona State University (Publisher)
Created2013
Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
ContributorsDessai, Gajanan (Author) / Gildenblat, Gennady (Committee member) / McAndrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
Ball Grid Array (BGA) using lead-free or lead-rich solder materials are widely used as Second Level Interconnects (SLI) in mounting packaged components to the printed circuit board (PCB). The reliability of these solder joints is of significant importance to the performance of microelectronics components and systems. Product design/form-factor, solder material, manufacturing process, use condition, as well as, the inherent variabilities present in the system, greatly influence product reliability. Accurate reliability analysis requires an integrated approach to concurrently account for all these factors and their synergistic effects. Such an integrated and robust methodology can be used in design and development of new and advanced microelectronics systems and can provide significant improvement in cycle-time, cost, and reliability. IMPRPK approach is based on a probabilistic methodology, focusing on three major tasks of (1) Characterization of BGA solder joints to identify failure mechanisms and obtain statistical data, (2) Finite Element analysis (FEM) to predict system response needed for life prediction, and (3) development of a probabilistic methodology to predict the reliability, as well as, the sensitivity of the system to various parameters and the variabilities. These tasks and the predictive capabilities of IMPRPK in microelectronic reliability analysis are discussed.
ContributorsFallah-Adl, Ali (Author) / Tasooji, Amaneh (Thesis advisor) / Krause, Stephen (Committee member) / Alford, Terry (Committee member) / Jiang, Hanqing (Committee member) / Mahajan, Ravi (Committee member) / Arizona State University (Publisher)
Created2013
Description
Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.
ContributorsYilmaz, Ender (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates.
ContributorsYang, Chengen (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2014
Description
With increasing demand for System on Chip (SoC) and System in Package (SiP) design in computer and communication technologies, integrated inductor which is an essential passive component has been widely used in numerous integrated circuits (ICs) such as in voltage regulators and RF circuits. In this work, soft ferromagnetic core material, amorphous Co-Zr-Ta-B, was incorporated into on-chip and in-package inductors in order to scale down inductors and improve inductors performance in both inductance density and quality factor. With two layers of 500 nm Co-Zr-Ta-B films a 3.5X increase in inductance and a 3.9X increase in quality factor over inductors without magnetic films were measured at frequencies as high as 1 GHz. By laminating technology, up to 9.1X increase in inductance and more than 5X increase in quality factor (Q) were obtained from stripline inductors incorporated with 50 nm by 10 laminated films with a peak Q at 300 MHz. It was also demonstrated that this peak Q can be pushed towards high frequency as far as 1GHz by a combination of patterning magnetic films into fine bars and laminations. The role of magnetic vias in magnetic flux and eddy current control was investigated by both simulation and experiment using different patterning techniques and by altering the magnetic via width. Finger-shaped magnetic vias were designed and integrated into on-chip RF inductors improving the frequency of peak quality factor from 400 MHz to 800 MHz without sacrificing inductance enhancement. Eddy current and magnetic flux density in different areas of magnetic vias were analyzed by HFSS 3D EM simulation. With optimized magnetic vias, high frequency response of up to 2 GHz was achieved. Furthermore, the effect of applied magnetic field on on-chip inductors was investigated for high power applications. It was observed that as applied magnetic field along the hard axis (HA) increases, inductance maintains similar value initially at low fields, but decreases at larger fields until the magnetic films become saturated. The high frequency quality factor showed an opposite trend which is correlated to the reduction of ferromagnetic resonant absorption in the magnetic film. In addition, experiments showed that this field-dependent inductance change varied with different patterned magnetic film structures, including bars/slots and fingers structures. Magnetic properties of Co-Zr-Ta-B films on standard organic package substrates including ABF and polyimide were also characterized. Effects of substrate roughness and stress were analyzed and simulated which provide strategies for integrating Co-Zr-Ta-B into package inductors and improving inductors performance. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on both ABF and polyimide substrates. Maximum 90% inductance increase in hundreds MHz frequency range were achieved in stripline inductors which are suitable for power delivery applications. Spiral inductors with Co-Zr-Ta-B films showed 18% inductance increase with quality factor of 4 at frequency up to 3 GHz.
ContributorsWu, Hao (Author) / Yu, Hongbin (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Chickamenahalli, Shamala (Committee member) / Arizona State University (Publisher)
Created2013
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
ContributorsSuh, Jounghyuk (Author) / Bakkaloglu, Bertan (Thesis advisor) / Cao, Yu (Committee member) / Ozev, Sule (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Organic optoelectronic devices have remained a research topic of great interest over the past two decades, particularly in the development of efficient organic photovoltaics (OPV) and organic light emitting diodes (OLED). In order to improve the efficiency, stability, and materials variety for organic optoelectronic devices a number of emitting materials, absorbing materials, and charge transport materials were developed and employed in a device setting. Optical, electrical, and photophysical studies of the organic materials and their corresponding devices were thoroughly carried out. Two major approaches were taken to enhance the efficiency of small molecule based OPVs: developing material with higher open circuit voltages or improved device structures which increased short circuit current. To explore the factors affecting the open circuit voltage (VOC) in OPVs, molecular structures were modified to bring VOC closer to the effective bandgap, ∆EDA, which allowed the achievement of 1V VOC for a heterojunction of a select Ir complex with estimated exciton energy of only 1.55eV. Furthermore, the development of anode interfacial layer for exciton blocking and molecular templating provide a general approach for enhancing the short circuit current. Ultimately, a 5.8% PCE was achieved in a single heterojunction of C60 and a ZnPc material prepared in a simple, one step, solvent free, synthesis. OLEDs employing newly developed deep blue emitters based on cyclometalated complexes were demonstrated. Ultimately, a peak EQE of 24.8% and nearly perfect blue emission of (0.148,0.079) was achieved from PtON7dtb, which approaches the maximum attainable performance from a blue OLED. Furthermore, utilizing the excimer formation properties of square-planar Pt complexes, highly efficient and stable white devices employing a single emissive material were demonstrated. A peak EQE of over 20% for pure white color (0.33,0.33) and 80 CRI was achieved with the tridentate Pt complex, Pt-16. Furthermore, the development of a series of tetradentate Pt complexes yielded highly efficient and stable single doped white devices due to their halogen free tetradentate design. In addition to these benchmark achievements, the systematic molecular modification of both emissive and absorbing materials provides valuable structure-property relationship information that should help guide further developments in the field.
ContributorsFleetham, Tyler Blain (Author) / Li, Jian (Thesis advisor) / Alford, Terry (Committee member) / Adams, James (Committee member) / Arizona State University (Publisher)
Created2014