Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
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- All Subjects: Radio--Transmitter-receivers.
- Creators: Bakkaloglu, Bertan
Description
The medical industry has benefited greatly by electronic integration resulting in the explosive growth of active medical implants. These devices often treat and monitor chronic health conditions and require very minimal power usage. A key part of these medical implants is an ultra-low power two way wireless communication system. This enables both control of the implant as well as relay of information collected. This research has focused on a high performance receiver for medical implant applications. One commonly quoted specification to compare receivers is energy per bit required. This metric is useful, but incomplete in that it ignores Sensitivity level, bit error rate, and immunity to interferers. In this study exploration of receiver architectures and convergence upon a comprehensive solution is done. This analysis is used to design and build a system for validation. The Direct Conversion Receiver architecture implemented for the MICS standard in 0.18 µm CMOS process consumes approximately 2 mW is competitive with published research.
ContributorsStevens, Mark (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively.
ContributorsKim, Sung (Author) / Bakkaloglu, Bertan (Thesis advisor) / Christen, Jennifer Blain (Committee member) / Cao, Yu (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010