Theses and Dissertations
This collection includes both ASU Theses and Dissertations, submitted by graduate students, and the Barrett, Honors College theses submitted by undergraduate students.
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Description
Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time.
ContributorsKilgore, Stephen (Author) / Adams, James (Thesis advisor) / Schroder, Dieter (Thesis advisor) / Krause, Stephen (Committee member) / Gaw, Craig (Committee member) / Arizona State University (Publisher)
Created2013
Description
The goal of this work is to develop low cost and highly efficient hybrid solar cells based on semiconductor nanoparticles (NPs). Hybrid solar cells have been demonstrated to take advantages of both inorganic and organic semiconductors by employing simple soluble process. In order to improve the power conversion efficiency (PCE), the bulk heterojunction (BHJ) of cadmium selenide (CdSe) tetrapods (TPs) and poly (3-hexylthiophene) (P3HT) are introduced as an electron acceptor and donor, respectively. The dimension of CdSe TPs and the 3D spatial distribution of CdSe TPs:P3HT photoactive blends are investigated to improve optical and electrical properties of photovoltaic devices. Hybrid solar cells having long-armed CdSe TPs and P3HT establish higher PCE of 1.12% when compared to device employing short-armed TPs of 0.80%. The device performance are improved by using longer armed CdSe TPs, which aids in better percolation connectivity and reduced charge hopping events, thus leading to better charge transport. The device architecture of hybrid solar cells is examined to assist vertical phase separation (VPS). Improvement of VPS in hybrid solar cells using CdSe TPs:P3HT photoactive blends is systematically manipulated by solution processed interfacial layers, resulting in enhanced device performance. Multi-layered hybrid solar cells assist better light absorption, efficient charge carrier transport, and increase of the surface contact area. In this work, hole transport assisting layer (HTAL)/BHJ photoactive layer (BPL)/electron transport assisting layer (ETAL) or HTAL/BPL/ETAL (HBE) multi-layered structure is introduced, similarly to p-type layer/intermixed photoactive layer
-type layer (p-i-n) structure of organic photovoltaic devices. To further control the improvement of the device performance, the effects of nano-scale morphology from solvents having different boiling points, the various shapes of semiconductor NPs, and the emergence of blending NPs are demonstrated. The formation of favorable 3D networks in photoactive layer is attributed to enhance the efficient charge transport by the optimized combination of semiconductor NPs in polymer matrix.
-type layer (p-i-n) structure of organic photovoltaic devices. To further control the improvement of the device performance, the effects of nano-scale morphology from solvents having different boiling points, the various shapes of semiconductor NPs, and the emergence of blending NPs are demonstrated. The formation of favorable 3D networks in photoactive layer is attributed to enhance the efficient charge transport by the optimized combination of semiconductor NPs in polymer matrix.
ContributorsLee, Kyu Sung (Author) / Jabbour, Ghassan E. (Thesis advisor) / Alford, Terry (Thesis advisor) / Krause, Stephen (Committee member) / Arizona State University (Publisher)
Created2012
Description
The semiconductor industry looks to constantly improve the efficiency of research and development in order to reduce costs and time to market. One such method was designed in order to decrease time spent inducing warpage in integrated circuits in an Intel research process. Intel's Atom product line seeks to compete with ARM architecture by entering the mobile devices CPU market. Due to the fundamental differences between the Atom's Bonnell architecture and the ARM architecture, the Intel Atom product line must utilize such improved research and development methods. Until power consumption is drastically lowered while maintaining processing speed, the Atom product line will not be able to effectively break into the mobile devices CPU market.
ContributorsLandseidel, Jack Adam (Author) / Adams, James (Thesis director) / Krause, Stephen (Committee member) / Anwar, Shahriar (Committee member) / Barrett, The Honors College (Contributor) / School of Mathematical and Statistical Sciences (Contributor) / Materials Science and Engineering Program (Contributor)
Created2013-05