ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 21 - 30 of 75
Description
Built-in-Self-Test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to do RF signal analysis. Existing on-chip resources, such as power or envelope detectors, or small additional circuitry can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as IQ imbalance, is challenging. In this work, a BiST technique to compute transmitter IQ imbalances using measurements out of a self-mixing envelope detector is proposed. Both the linear and non linear parameters of the RF transmitter path are extracted successfully. We first derive an analytical expression for the output signal. Using this expression, we devise test signals to isolate the effects of gain and phase imbalance, DC offsets, time skews and system nonlinearity from other parameters of the system. Once isolated, these parameters are calculated easily with a few mathematical operations. Simulations and hardware measurements show that the technique can provide accurate characterization of IQ imbalances. One of the glaring advantages of this method is that, the impairments are extracted from analyzing the response at baseband frequency and thereby eliminating the need of high frequency ATE (Automated Test Equipment).
ContributorsByregowda, Srinath (Author) / Ozev, Sule (Thesis advisor) / Cao, Yu (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis summarizes the research work carried out on design, modeling and simulation of semiconductor nanophotonic devices. The research includes design of nanowire (NW) lasers, modeling of active plasmonic waveguides, design of plasmonic nano-lasers, and design of all-semiconductor plasmonic systems. For the NW part, a comparative study of electrical injection in the longitudinal p-i-n and coaxial p-n core-shell NWs was performed. It is found that high density carriers can be efficiently injected into and confined in the core-shell structure. The required bias voltage and doping concentrations in the core-shell structure are smaller than those in the longitudinal p-i-n structure. A new device structure with core-shell configuration at the p and n contact regions for electrically driven single NW laser was proposed. Through a comprehensive design trade-off between threshold gain and threshold voltage, room temperature lasing has been proved in the laser with low threshold current and large output efficiency. For the plasmonic part, the propagation of surface plasmon polariton (SPP) in a metal-semiconductor-metal structure where semiconductor is highly excited to have an optical gain was investigated. It is shown that near the resonance the SPP mode experiences an unexpected giant modal gain that is 1000 times of the material gain in the semiconductor and the corresponding confinement factor is as high as 105. The physical origin of the giant modal gain is the slowing down of the average energy propagation in the structure. Secondly, SPP modes lasing in a metal-insulator-semiconductor multi-layer structure was investigated. It is shown that the lasing threshold can be reduced by structural optimization. A specific design example was optimized using AlGaAs/GaAs/AlGaAs single quantum well sandwiched between silver layers. This cavity has a physical volume of 1.5×10-4 λ03 which is the smallest nanolaser reported so far. Finally, the all-semiconductor based plasmonics was studied. It is found that InAs is superior to other common semiconductors for plasmonic application in mid-infrared range. A plasmonic system made of InAs, GaSb and AlSb layers, consisting of a plasmonic source, waveguide and detector was proposed. This on-chip integrated system is realizable in a single epitaxial growth process.
ContributorsLi, Debin (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Balanis, Constantine A (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
Nanowires (NWs) have attracted many interests due to their advance in synthesis and their unique structural, electrical and optical properties. NWs have been realized as promising candidates for future photonic platforms. In this work, erbium chloride silicate (ECS), CdS and CdSSe NWs growth by vapor-liquid-solid mechanism and their characterization were demonstrated. In the ECS NWs part, systematic experiments were performed to investigate the relation between growth temperature and NWs structure. Scanning electron microscopy, Raman spectroscopy, X-ray diffraction and photoluminescence characterization were used to study the NWs morphology, crystal quality and optical properties. At low growth temperature, there was strong Si Raman signal observed indicating ECS NWs have Si core. At high growth temperature, the excess Si signal was disappeared and the NWs showed better crystal quality and optical properties. The growth temperature is the key parameter that will induce the transition from Si/ECS core-shell NWs structure to solid ECS NWs. With the merits of high Er concentration and long PL lifetime, ECS NWs can serve as optical gain material with emission at 1.5 μm for communications and amplifiers. In the CdS, CdSSe NWs part, the band gap engineering of CdSSe NWs with spatial composition tuning along single NWs were demonstrated. The first step of realizing CdSSe NWs was the controlled growth of CdS NWs. It showed that overall pressure would largely affect the lengths of the CdS NWs. NWs with longer length can be obtained at higher pressure. Then, based on CdS NWs growth and by adding CdSe step by step, composition graded CdSSe alloy NWs were successfully synthesized. The temperature control over the source vapor concentration plays the key role for the growth.
ContributorsNing, Hao (Author) / Ning, Cunzheng (Thesis advisor) / Yu, Hongbin (Committee member) / Zhang, Yong-Hang (Committee member) / Arizona State University (Publisher)
Created2012
Description
What can classical chaos do to quantum systems is a fundamental issue highly relevant to a number of branches in physics. The field of quantum chaos has been active for three decades, where the focus was on non-relativistic quantumsystems described by the Schr¨odinger equation. By developing an efficient method to solve the Dirac equation in the setting where relativistic particles can tunnel between two symmetric cavities through a potential barrier, chaotic cavities are found to suppress the spread in the tunneling rate. Tunneling rate for any given energy assumes a wide range that increases with the energy for integrable classical dynamics. However, for chaotic underlying dynamics, the spread is greatly reduced. A remarkable feature, which is a consequence of Klein tunneling, arise only in relativistc quantum systems that substantial tunneling exists even for particle energy approaching zero. Similar results are found in graphene tunneling devices, implying high relevance of relativistic quantum chaos to the development of such devices. Wave propagation through random media occurs in many physical systems, where interesting phenomena such as branched, fracal-like wave patterns can arise. The generic origin of these wave structures is currently a matter of active debate. It is of fundamental interest to develop a minimal, paradigmaticmodel that can generate robust branched wave structures. In so doing, a general observation in all situations where branched structures emerge is non-Gaussian statistics of wave intensity with an algebraic tail in the probability density function. Thus, a universal algebraic wave-intensity distribution becomes the criterion for the validity of any minimal model of branched wave patterns. Coexistence of competing species in spatially extended ecosystems is key to biodiversity in nature. Understanding the dynamical mechanisms of coexistence is a fundamental problem of continuous interest not only in evolutionary biology but also in nonlinear science. A continuous model is proposed for cyclically competing species and the effect of the interplay between the interaction range and mobility on coexistence is investigated. A transition from coexistence to extinction is uncovered with a non-monotonic behavior in the coexistence probability and switches between spiral and plane-wave patterns arise. Strong mobility can either promote or hamper coexistence, while absent in lattice-based models, can be explained in terms of nonlinear partial differential equations.
ContributorsNi, Xuan (Author) / Lai, Ying-Cheng (Thesis advisor) / Huang, Liang (Committee member) / Yu, Hongbin (Committee member) / Akis, Richard (Committee member) / Arizona State University (Publisher)
Created2012
Description
Recently a new materials platform consisting of semiconductors grown on GaSb and InAs substrates with lattice constants close to 6.1 A was proposed by our group for various electronic and optoelectronic applications. This materials platform consists of both II-VI (MgZnCdHg)(SeTe) and III-V (InGaAl)(AsSb) compound semiconductors, which have direct bandgaps spanning the entire energy spectrum from far-IR (~0 eV) up to UV (~3.4 eV). The broad range of bandgaps and material properties make it very attractive for a wide range of applications in optoelectronics, such as solar cells, laser diodes, light emitting diodes, and photodetectors. Moreover, this novel materials system potentially offers unlimited degrees of freedom for integration of electronic and optoelectronic devices onto a single substrate while keeping the best possible materials quality with very low densities of misfit dislocations. This capability is not achievable with any other known lattice-matched semiconductors on any available substrate. In the 6.1-A materials system, the semiconductors ZnTe and GaSb are almost perfectly lattice-matched with a lattice mismatch of only 0.13%. Correspondingly, it is expected that high quality ZnTe/GaSb and GaSb/ZnTe heterostructures can be achieved with very few dislocations generated during growth. To fulfill the task, their MBE growth and material properties are carefully investigated. High quality ZnTe layers grown on various III-V substrates and GaSb grown on ZnTe are successfully achieved using MBE. It is also noticed that ZnTe and GaSb have a type-I band-edge alignment with large band offsets (delta_Ec=0.934 eV, delta_Ev=0.6 eV), which provides strong confinement for both electrons and holes. Furthermore, a large difference in refractive index is found between ZnTe and GaSb (2.7 and 3.9, respectively, at 0.7 eV), leading to excellent optical confinement of the guided optical modes in planar semiconductor lasers or distributed Bragg reflectors (DBR) for vertical-cavity surface-emitting lasers. Therefore, GaSb/ZnTe double-heterostructure and ZnTe/GaSb DBR structure are suitable for use in light emitting devices. In this thesis work, experimental demonstration of these structures with excellent structural and optical properties is reported. During the exploration on the properties of various ZnTe heterostructures, it is found that residual tensile strains exist in the thick ZnTe epilayers when they are grown on GaAs, InP, InAs and GaSb substrates. The presence of tensile strains is due to the difference in thermal expansion coefficients between the epilayers and the substrates. The defect densities in these ZnTe layers become lower as the ZnTe layer thickness increases. Growth of high quality GaSb on ZnTe can be achieved using a temperature ramp during growth. The influence of temperature ramps with different ramping rates in the optical properties of GaSb layer is studied, and the samples grown with a temperature ramp from 360 to 470 C at a rate of 33 C/min show the narrowest bound exciton emission peak with a full width at half maximum of 15 meV. ZnTe/GaSb DBR structures show excellent reflectivity properties in the mid-infrared range. A peak reflectance of 99% with a wide stopband of 480 nm centered at 2.5 um is measured from a ZnTe/GaSb DBR sample of only 7 quarter-wavelength pairs.
ContributorsFan, Jin (Author) / Zhang, Yong-Hang (Thesis advisor) / Smith, David (Committee member) / Yu, Hongbin (Committee member) / Menéndez, Jose (Committee member) / Johnson, Shane (Committee member) / Arizona State University (Publisher)
Created2012
Description
Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and Dynamic Voltage Scaling (DVS) in real circuit operation. To overcome these barriers, the modeling effort in this work (1) practically explains the aging statistics due to randomness in number of traps with log(t) model, accurately predicting the mean and variance shift; (2) proposes cycle-to-cycle model (from the first-principle of trapping) to handle aging under multiple supply voltages, predicting the non-monotonic behavior under DVS (3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles, and (4) comprehensively validates the new set of aging models with 65nm statistical silicon data. Compared to previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard-banding during the design stage. With CMOS technology scaling, design for reliability has become an important step in the design cycle, and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI induced delay shifts in logic paths are asymmetric in nature, as opposed to averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this report, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of the simulation flow include: (1) accurate modeling of aging induced delay shift due to threshold voltage (Vth) shift using only the delay dependence on supply voltage from cell library; (2) simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; (3) setup and hold timing violations due to NBTI aging in logic and clock buffer are investigated in sequential circuits and (4) proposed framework is tested in VLSI applications such DDR memory circuits. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45nm Nangate standard cell library characterized using predictive technology models. Our proposed design margin assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.
ContributorsVelamala, Jyothi Bhaskarr (Author) / Cao, Yu (Thesis advisor) / Clark, Lawrence (Committee member) / Chakrabarti, Chaitali (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Description
This thesis mainly focuses on the study of quantum efficiency (QE) and its measurement, especially for nanowires (NWs). First, a brief introduction of nano-technology and nanowire is given to describe my initial research interest. Next various fundamental kinds of recombination mechanisms are described; both for radiative and non-radiative processes. This is an introduction for defining the internal quantum efficiency (IQE). A relative IQE measurement method is shown following that. Then it comes to the major part of the thesis discussing a procedure of quantum efficiency measurement using photoluminescence (PL) method and an integrating sphere, which has not been much applied to nanowires (NWs). In fact this is a convenient and useful approach for evaluating the quality of NWs since it considers not only the PL emission but also the absorption of NWs. The process is well illustrated and performed with both wavelength-dependent and power-dependent measurements. The measured PLQE is in the range of 0.3% ~ 5.4%. During the measurement, a phenomenon called photodegradation is observed and examined by a set of power-dependence measurements. This effect can be a factor for underestimating the PLQE and a procedure is introduced during the sample preparation process which managed to reduce this effect for some degree.
ContributorsChen, Dongzi (Author) / Ning, Cun-Zheng (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2012
Towards high-efficiency thin-film solar cells: from theoretical analysis to experimental exploration
Description
GaAs single-junction solar cells have been studied extensively in recent years, and have reached over 28 % efficiency. Further improvement requires an optically thick but physically thin absorber to provide both large short-circuit current and high open-circuit voltage. By detailed simulation, it is concluded that ultra-thin GaAs cells with hundreds of nanometers thickness and reflective back scattering can potentially offer efficiencies greater than 30 %. The 300 nm GaAs solar cell with AlInP/Au reflective back scattering is carefully designed and demonstrates an efficiency of 19.1 %. The device performance is analyzed using the semi-analytical model with Phong distribution implemented to account for non-Lambertian scattering. A Phong exponent m of ~12, a non-radiative lifetime of 130 ns, and a specific series resistivity of 1.2 Ω·cm2 are determined.
Thin-film CdTe solar cells have also attracted lots of attention due to the continuous improvements in their device performance. To address the issue of the lower efficiency record compared to detailed-balance limit, the single-crystalline Cd(Zn)Te/MgCdTe double heterostructures (DH) grown on InSb (100) substrates by molecular beam epitaxy (MBE) are carefully studied. The Cd0.9946Zn0.0054Te alloy lattice-matched to InSb has been demonstrated with a carrier lifetime of 0.34 µs observed in a 3 µm thick Cd0.9946Zn0.0054Te/MgCdTe DH sample. The substantial improvement of lifetime is due to the reduction in misfit dislocation density. The recombination lifetime and interface recombination velocity (IRV) of CdTe/MgxCd1-xTe DHs are investigated. The IRV is found to be dependent on both the MgCdTe barrier height and width due to the thermionic emission and tunneling processes. A record-long carrier lifetime of 2.7 µs and a record-low IRV of close to zero have been confirmed experimentally.
The MgCdTe/Si tandem solar cell is proposed to address the issue of high manufacturing costs and poor performance of thin-film solar cells. The MBE grown MgxCd1-xTe/MgyCd1-yTe DHs have demonstrated the required bandgap energy of 1.7 eV, a carrier lifetime of 11 ns, and an effective IRV of (1.869 ± 0.007) × 103 cm/s. The large IRV is attributed to thermionic-emission induced interface recombination. These understandings can be applied to fabricating the high-efficiency low-cost MgCdTe/Si tandem solar cell.
Thin-film CdTe solar cells have also attracted lots of attention due to the continuous improvements in their device performance. To address the issue of the lower efficiency record compared to detailed-balance limit, the single-crystalline Cd(Zn)Te/MgCdTe double heterostructures (DH) grown on InSb (100) substrates by molecular beam epitaxy (MBE) are carefully studied. The Cd0.9946Zn0.0054Te alloy lattice-matched to InSb has been demonstrated with a carrier lifetime of 0.34 µs observed in a 3 µm thick Cd0.9946Zn0.0054Te/MgCdTe DH sample. The substantial improvement of lifetime is due to the reduction in misfit dislocation density. The recombination lifetime and interface recombination velocity (IRV) of CdTe/MgxCd1-xTe DHs are investigated. The IRV is found to be dependent on both the MgCdTe barrier height and width due to the thermionic emission and tunneling processes. A record-long carrier lifetime of 2.7 µs and a record-low IRV of close to zero have been confirmed experimentally.
The MgCdTe/Si tandem solar cell is proposed to address the issue of high manufacturing costs and poor performance of thin-film solar cells. The MBE grown MgxCd1-xTe/MgyCd1-yTe DHs have demonstrated the required bandgap energy of 1.7 eV, a carrier lifetime of 11 ns, and an effective IRV of (1.869 ± 0.007) × 103 cm/s. The large IRV is attributed to thermionic-emission induced interface recombination. These understandings can be applied to fabricating the high-efficiency low-cost MgCdTe/Si tandem solar cell.
ContributorsLiu, Shi (Author) / Zhang, Yong-Hang (Thesis advisor) / Johnson, Shane R (Committee member) / Vasileska, Dragica (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
Solid-state nanopore research, used in the field of biomolecule detection and separation, has developed rapidly during the last decade. An electric field generated from the nanopore membrane to the aperture surface by a bias voltage can be used to electrostatically control the transport of charges. This results in ionic current rectification that can be used for applications such as biomolecule filtration and DNA sequencing.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
ContributorsWang, Xiaofeng (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Christen, Jennifer M (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
The microelectronics technology has seen a tremendous growth over the past sixty years. The advancements in microelectronics, which shows the capability of yielding highly reliable and reproducible structures, have made the mass production of integrated electronic components feasible. Miniaturized, low-cost, and accurate sensors became available due to the rise of the microelectronics industry. A variety of sensors are being used extensively in many portable applications. These sensors are promising not only in research area but also in daily routine applications.
However, many sensing systems are relatively bulky, complicated, and expensive and main advantages of new sensors do not play an important role in practical applications. Many challenges arise due to intricacies for sensor packaging, especially operation in a solution environment. Additional problems emerge when interfacing sensors with external off-chip components. A large amount of research in the field of sensors has been focused on how to improve the system integration.
This work presents new methods for the design, fabrication, and integration of sensor systems. This thesis addresses these challenges, for example, interfacing microelectronic system to a liquid environment and developing a new technique for impedimetric measurement. This work also shows a new design for on-chip optical sensor without any other extra components or post-processing.
However, many sensing systems are relatively bulky, complicated, and expensive and main advantages of new sensors do not play an important role in practical applications. Many challenges arise due to intricacies for sensor packaging, especially operation in a solution environment. Additional problems emerge when interfacing sensors with external off-chip components. A large amount of research in the field of sensors has been focused on how to improve the system integration.
This work presents new methods for the design, fabrication, and integration of sensor systems. This thesis addresses these challenges, for example, interfacing microelectronic system to a liquid environment and developing a new technique for impedimetric measurement. This work also shows a new design for on-chip optical sensor without any other extra components or post-processing.
ContributorsLuo, Tao (Author) / Blain Christen, Jennifer (Thesis advisor) / Song, Hongjiang (Committee member) / Goryll, Michael (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015