ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
Although there have been many attempts to adapt EIP methodology to existing industrial sharing networks, most of them have failed for various factors: geographic restrictions by governmental organizations on use of technology, cost of technology, the inability of industries to effectively communicate their upstream and downstream resource usage, and to diminishing natural resources such as water, land and non-renewable energy (NRE) sources for energy production.
This paper presents a feasibility study conducted to evaluate the comparative environmental, economic, and geographic impacts arising from the use of renewable energy (RE) and NRE to power EIPs. Life Cycle Assessment (LCA) methodology, which is used in a variety of sectors to evaluate the environmental merits and demerits of different kinds of products and processes, was employed for comparison between these two energy production methods based on factors such as greenhouse gas emission, acidification potential, eutrophication potential, human toxicity potential, fresh water usage and land usage. To complement the environmental LCA analysis, levelized cost of electricity was used to evaluate the economic impact. This model was analyzed for two different geographic locations; United States and Europe, for 12 different energy production technologies.
The outcome of this study points out the environmental, economic and geographic superiority of one energy source over the other, including the total carbon dioxide equivalent emissions, which can then be related to the total number of carbon credits that can be earned or used to mitigate the overall carbon emission and move closer towards a net zero carbon footprint goal thus making the EIPs truly sustainable.
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.