ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 77
Description
Switch mode DC/DC converters are suited for battery powered applications, due to their high efficiency, which help in conserving the battery lifetime. Fixed Frequency PWM based converters, which are generally used for these applications offer good voltage regulation, low ripple and excellent efficiency at high load currents. However at light load currents, fixed frequency PWM converters suffer from poor efficiencies The PFM control offers higher efficiency at light loads at the cost of a higher ripple. The PWM has a poor efficiency at light loads but good voltage ripple characteristics, due to a high switching frequency. To get the best of both control modes, both loops are used together with the control switched from one loop to another based on the load current. Such architectures are referred to as hybrid converters. While transition from PFM to PWM loop can be made by estimating the average load current, transition from PFM to PWM requires voltage or peak current sensing. This theses implements a hysteretic PFM solution for a synchronous buck converter with external MOSFET's, to achieve efficiencies of about 80% at light loads. As the PFM loop operates independently of the PWM loop, a transition circuit for automatically transitioning from PFM to PWM is implemented. The transition circuit is implemented digitally without needing any external voltage or current sensing circuit.
ContributorsVivek, Parasuram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2014
Description
ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed.
ContributorsKumar, Sushil (Author) / Clark, Lawrence (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
In this research, our goal was to fabricate Josephson junctions that can be stably processed at 300°C or higher. With the purpose of integrating Josephson junction fabrication with the current semiconductor circuit fabrication process, back-end process temperatures (>350 °C) will be a key for producing large scale junction circuits reliably, which requires the junctions to be more thermally stable than current Nb/Al-AlOx/Nb junctions. Based on thermodynamics, Hf was chosen to produce thermally stable Nb/Hf-HfOx/Nb superconductor tunnel Josephson junctions that can be grown or processed at elevated temperatures. Also elevated synthesis temperatures improve the structural and electrical properties of Nb electrode layers that could potentially improve junction device performance. The refractory nature of Hf, HfO2 and Nb allow for the formation of flat, abrupt and thermally-stable interfaces. But the current Al-based barrier will have problems when using with high-temperature grown and high-quality Nb. So our work is aimed at using Nb grown at elevated temperatures to fabricate thermally stable Josephson tunnel junctions. As a junction barrier metal, Hf was studied and compared with the traditional Al-barrier material. We have proved that Hf-HfOx is a good barrier candidate for high-temperature synthesized Josephson junction. Hf deposited at 500 °C on Nb forms flat and chemically abrupt interfaces. Nb/Hf-HfOx/Nb Josephson junctions were synthesized, fabricated and characterized with different oxidizing conditions. The results of materials characterization and junction electrical measurements are reported and analyzed. We have improved the annealing stability of Nb junctions and also used high-quality Nb grown at 500 °C as the bottom electrode successfully. Adding a buffer layer or multiple oxidation steps improves the annealing stability of Josephson junctions. We also have attempted to use the Atomic Layer Deposition (ALD) method for the growth of Hf oxide as the junction barrier and got tunneling results.
ContributorsHuang, Mengchu, 1987- (Author) / Newman, Nathan (Thesis advisor) / Rowell, John M. (Committee member) / Singh, Rakesh K. (Committee member) / Chamberlin, Ralph (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2013
Description
Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates.
ContributorsYang, Chengen (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2014
Description
The research objective is fully differential op-amp with common mode feedback, which are applied in filter, band gap, Analog Digital Converter (ADC) and so on as a fundamental component in analog circuit. Having modeled various defect and analyzed corresponding probability, defect library could be built after reduced defect simulation.Based on the resolution of microscope scan tool, all these defects are categorized into four groups of defects by both function and location, bias circuit defect, first stage amplifier defect, output stage defect and common mode feedback defect, separately. Each fault result is attributed to one of these four region defects.Therefore, analog testing algorithm and automotive tool could be generated to assist testing engineers to meet the demand of large numbers of chips.
ContributorsLu, Zhijian (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Three dimensional (3-D) ultrasound is safe, inexpensive, and has been shown to drastically improve system ease-of-use, diagnostic efficiency, and patient throughput. However, its high computational complexity and resulting high power consumption has precluded its use in hand-held applications.
In this dissertation, algorithm-architecture co-design techniques that aim to make hand-held 3-D ultrasound a reality are presented. First, image enhancement methods to improve signal-to-noise ratio (SNR) are proposed. These include virtual source firing techniques and a low overhead digital front-end architecture using orthogonal chirps and orthogonal Golay codes.
Second, algorithm-architecture co-design techniques to reduce the power consumption of 3-D SAU imaging systems is presented. These include (i) a subaperture multiplexing strategy and the corresponding apodization method to alleviate the signal bandwidth bottleneck, and (ii) a highly efficient iterative delay calculation method to eliminate complex operations such as multiplications, divisions and square-root in delay calculation during beamforming. These techniques were used to define Sonic Millip3De, a 3-D die stacked architecture for digital beamforming in SAU systems. Sonic Millip3De produces 3-D high resolution images at 2 frames per second with system power consumption of 15W in 45nm technology.
Third, a new beamforming method based on separable delay decomposition is proposed to reduce the computational complexity of the beamforming unit in an SAU system. The method is based on minimizing the root-mean-square error (RMSE) due to delay decomposition. It reduces the beamforming complexity of a SAU system by 19x while providing high image fidelity that is comparable to non-separable beamforming. The resulting modified Sonic Millip3De architecture supports a frame rate of 32 volumes per second while maintaining power consumption of 15W in 45nm technology.
Next a 3-D plane-wave imaging system that utilizes both separable beamforming and coherent compounding is presented. The resulting system has computational complexity comparable to that of a non-separable non-compounding baseline system while significantly improving contrast-to-noise ratio and SNR. The modified Sonic Millip3De architecture is now capable of generating high resolution images at 1000 volumes per second with 9-fire-angle compounding.
In this dissertation, algorithm-architecture co-design techniques that aim to make hand-held 3-D ultrasound a reality are presented. First, image enhancement methods to improve signal-to-noise ratio (SNR) are proposed. These include virtual source firing techniques and a low overhead digital front-end architecture using orthogonal chirps and orthogonal Golay codes.
Second, algorithm-architecture co-design techniques to reduce the power consumption of 3-D SAU imaging systems is presented. These include (i) a subaperture multiplexing strategy and the corresponding apodization method to alleviate the signal bandwidth bottleneck, and (ii) a highly efficient iterative delay calculation method to eliminate complex operations such as multiplications, divisions and square-root in delay calculation during beamforming. These techniques were used to define Sonic Millip3De, a 3-D die stacked architecture for digital beamforming in SAU systems. Sonic Millip3De produces 3-D high resolution images at 2 frames per second with system power consumption of 15W in 45nm technology.
Third, a new beamforming method based on separable delay decomposition is proposed to reduce the computational complexity of the beamforming unit in an SAU system. The method is based on minimizing the root-mean-square error (RMSE) due to delay decomposition. It reduces the beamforming complexity of a SAU system by 19x while providing high image fidelity that is comparable to non-separable beamforming. The resulting modified Sonic Millip3De architecture supports a frame rate of 32 volumes per second while maintaining power consumption of 15W in 45nm technology.
Next a 3-D plane-wave imaging system that utilizes both separable beamforming and coherent compounding is presented. The resulting system has computational complexity comparable to that of a non-separable non-compounding baseline system while significantly improving contrast-to-noise ratio and SNR. The modified Sonic Millip3De architecture is now capable of generating high resolution images at 1000 volumes per second with 9-fire-angle compounding.
ContributorsYang, Ming (Author) / Chakrabarti, Chaitali (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Karam, Lina (Committee member) / Frakes, David (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
Switching Converters (SC) are an excellent choice for hand held devices due to their high power conversion efficiency. However, they suffer from two major drawbacks. The first drawback is that their dynamic response is sensitive to variations in inductor (L) and capacitor (C) values. A cost effective solution is implemented by designing a programmable digital controller. Despite variations in L and C values, the target dynamic response can be achieved by computing and programming the filter coefficients for a particular L and C. Besides, digital controllers have higher immunity to environmental changes such as temperature and aging of components. The second drawback of SCs is their poor efficiency during low load conditions if operated in Pulse Width Modulation (PWM) mode. However, if operated in Pulse Frequency Modulation (PFM) mode, better efficiency numbers can be achieved. A mostly-digital way of detecting PFM mode is implemented. Besides, a slow serial interface to program the chip, and a high speed serial interface to characterize mixed signal blocks as well as to ship data in or out for debug purposes are designed. The chip is taped out in 0.18µm IBM's radiation hardened CMOS process technology. A test board is built with the chip, external power FETs and driver IC. At the time of this writing, PWM operation, PFM detection, transitions between PWM and PFM, and both serial interfaces are validated on the test board.
ContributorsMumma Reddy, Abhiram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
Register file (RF) memory is important in low power system on chip (SOC) due to its
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.
ContributorsVashishtha, Vinay (Author) / Clark, Lawrence T. (Thesis advisor) / Seo, Jae-Sun (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
The ability to shift the photovoltaic (PV) power curve and make the energy accessible during peak hours can be accomplished through pairing solar PV with energy storage technologies. A prototype hybrid air conditioning system (HACS), built under supervision of project head Patrick Phelan, consists of PV modules running a DC compressor that operates a conventional HVAC system paired with a second evaporator submerged within a thermal storage tank. The thermal storage is a 0.284m3 or 75 gallon freezer filled with Cryogel balls, submerged in a weak glycol solution. It is paired with its own separate air handler, circulating the glycol solution. The refrigerant flow is controlled by solenoid valves that are electrically connected to a high and low temperature thermostat. During daylight hours, the PV modules run the DC compressor. The refrigerant flow is directed to the conventional HVAC air handler when cooling is needed. Once the desired room temperature is met, refrigerant flow is diverted to the thermal storage, storing excess PV power. During peak energy demand hours, the system uses only small amounts of grid power to pump the glycol solution through the air handler (note the compressor is off), allowing for money and energy savings. The conventional HVAC unit can be scaled down, since during times of large cooling demands the glycol air handler can be operated in parallel with the conventional HVAC unit. Four major test scenarios were drawn up in order to fully comprehend the performance characteristics of the HACS. Upon initial running of the system, ice was produced and the thermal storage was charged. A simple test run consisting of discharging the thermal storage, initially ~¼ frozen, was performed. The glycol air handler ran for 6 hours and the initial cooling power was 4.5 kW. This initial test was significant, since greater than 3.5 kW of cooling power was produced for 3 hours, thus demonstrating the concept of energy storage and recovery.
ContributorsPeyton-Levine, Tobin (Author) / Phelan, Patrick (Thesis advisor) / Trimble, Steve (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2012
Description
The study of high energy particle irradiation effect on Josephson junction tri-layers is relevant to applications in space and radioactive environments. It also allows us to investigate the influence of defects and interfacial intermixing on the junction electrical characteristics. In this work, we studied the influence of 2MeV Helium ion irradiation with doses up to 5.2×1016 ions/cm2 on the tunneling behavior of Nb/Al/AlOx/Nb Josephson junctions. Structural and analytical TEM characterization, combined with SRIM modeling, indicates that over 4nm of intermixing occurred at the interfaces. EDX analysis after irradiation, suggests that the Al and O compositions from the barrier are collectively distributed together over a few nanometers. Surprisingly, the IV characteristics were largely unchanged. The normal resistance, Rn, increased slightly (<20%) after the initial dose of 3.5×1015 ions/cm2 and remained constant after that. This suggests that tunnel barrier electrical properties were not affected much, despite the significant changes in the chemical distribution of the barrier's Al and O shown in SRIM modeling and TEM pictures. The onset of quasi-particle current, sum of energy gaps (2Δ), dropped systematically from 2.8meV to 2.6meV with increasing dosage. Similarly, the temperature onset of the Josephson current dropped from 9.2K to 9.0K. This suggests that the order parameter at the barrier interface has decreased as a result of a reduced mean free path in the Al proximity layer and a reduction in the transition temperature of the Nb electrode near the barrier. The dependence of Josephson current on the magnetic field and temperature does not change significantly with irradiation, suggesting that intermixing into the Nb electrode is significantly less than the penetration depth.
ContributorsZhang, Tiantian (Author) / Newman, Nathan (Thesis advisor) / Rowell, John M (Committee member) / Singh, Rakesh K. (Committee member) / Chamberlin, Ralph (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2012