ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 41 - 50 of 56
Description
The development of portable electronic systems has been a fundamental factor to the emergence of new applications including ubiquitous smart devices, self-driving vehicles. Power-Management Integrated Circuits (PMICs) which are a key component of such systems must maintain high efficiency and reliability for the final system to be appealing from a size and cost perspective. As technology advances, such portable systems require high output currents at low voltages from their PMICs leading to thermal reliability concerns. The reliability and power integrity of PMICs in such systems also degrades when operated in harsh environments. This dissertation presents solutions to solve two such reliability problems.The first part of this work presents a scalable, daisy-chain solution to parallelize multiple low-dropout linear (LDO) regulators to increase the total output current at low voltages. This printed circuit board (PCB) friendly approach achieves output current sharing without the need for any off-chip active or passive components or matched PCB traces thus reducing the overall system cost. Fully integrated current sensing based on dynamic element matching eliminates the need for any off-chip current sensing components. A current sharing accuracy of 2.613% and 2.789% for output voltages of 3V and 1V respectively and an output current of 2A per LDO are measured for the parallel LDO system implemented in a 0.18μm process. Thermal images demonstrate that the parallel LDO system achieves thermal equilibrium and stable reliable operation.
The remainder of the thesis deals with time-domain switching regulators for high-reliability applications. A time-domain based buck and boost controller with time as the processing variable is developed for use in harsh environments. The controller features adaptive on-time / off-time generation for quasi-constant switching frequency and a time-domain comparator to implement current-mode hysteretic control. A triple redundant bandgap reference is also developed to mitigate the effects of radiation. Measurement results are showcased for a buck and boost converter with a common controller IC implemented in a 0.18μm process and an external power stage. The converter achieves a peak efficiency of 92.22% as a buck for an output current of 5A and an output voltage of 5V. Similarly, the converter achieves an efficiency of 95.97% as a boost for an output current of 1.25A and an output voltage of 30.4V.
ContributorsTalele, Bhushan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Seo, Jae-Sun (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2021
Description
Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ContributorsPraveen, Subramanya Chilukuri (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Long, Yu (Committee member) / Arizona State University (Publisher)
Created2019
Description
High-efficiency DC-DC converters make up one of the important blocks of state-of-the-art power supplies. The trend toward high level of transistor integration has caused load current demands to grow significantly. Supplying high output current and minimizing output current ripple has been a driving force behind the evolution of Multi-phase topologies. Ability to supply large output current with improved efficiency, reduction in the size of filter components, improved transient response make multi-phase topologies a preferred choice for low voltage-high current applications.
Current sensing capability inside a system is much sought after for applications which include Peak-current mode control, Current limiting, Overload protection. Current sensing is extremely important for current sharing in Multi-phase topologies. Existing approaches such as Series resistor, SenseFET, inductor DCR based current sensing are simple but their drawbacks such low efficiency, low accuracy, limited bandwidth demand a novel current sensing scheme.
This research presents a systematic design procedure of a 5V - 1.8V, 8A 4-Phase Buck regulator with a novel current sensing scheme based on replication of the inductor current. The proposed solution consists of detailed system modeling in PLECS which includes modification of the peak current mode model to accommodate the new current sensing element, derivation of power-stage and Plant transfer functions, Controller design. The proposed model has been verified through PLECS simulations and compared with a transistor-level implementation of the system. The time-domain parameters such as overshoot and settling-time simulated through transistor-level
implementation is in close agreement with the results obtained from the PLECS model.
Current sensing capability inside a system is much sought after for applications which include Peak-current mode control, Current limiting, Overload protection. Current sensing is extremely important for current sharing in Multi-phase topologies. Existing approaches such as Series resistor, SenseFET, inductor DCR based current sensing are simple but their drawbacks such low efficiency, low accuracy, limited bandwidth demand a novel current sensing scheme.
This research presents a systematic design procedure of a 5V - 1.8V, 8A 4-Phase Buck regulator with a novel current sensing scheme based on replication of the inductor current. The proposed solution consists of detailed system modeling in PLECS which includes modification of the peak current mode model to accommodate the new current sensing element, derivation of power-stage and Plant transfer functions, Controller design. The proposed model has been verified through PLECS simulations and compared with a transistor-level implementation of the system. The time-domain parameters such as overshoot and settling-time simulated through transistor-level
implementation is in close agreement with the results obtained from the PLECS model.
ContributorsBurli, Venkatesh (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2017
Description
With the push for integration, a slew of modern switching power management circuits are operating at higher switching frequencies in order to reduce passive filter sizes. But while these switching regulators provide power conversion at high efficiencies, their output is prone to ripples due to the inherent switching behavior. These switching regulators use linear-low dropout regulators (LDOs) downstream to provide clean supplies. Typically, these LDOs have good power supply rejection (PSR) at lower frequencies but this degrades at higher frequencies. Therefore, some residual ripple is still manifested on the output. Because of this, high power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems- on-chip (SOCs).
Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop- bandwidth. The LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system- level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1μs and has a quiescent current of 5.6μA. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 mV and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing.
Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop- bandwidth. The LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system- level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1μs and has a quiescent current of 5.6μA. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 mV and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing.
ContributorsJoshi, Kishan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Seo, Jae-Sun (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2020
Description
In this work, the development of a novel and a truly in-shoe force measurement system is reported. The device consists of a shoe insole with six thin film piezoresistive sensors and the main circuit board. The piezoresistive sensors are used for the measurement of plantar pressure during daily human activities. The motion sensor mounted on the main circuit board captures kinematic data. In addition, the main circuit board is responsible for the wireless transmission of the data from all the sensors in real-time using BLE protocol. It is housed within the midsole of the shoe, under the medial arch of the foot. The real-time quantitative data and its analyses, enables athletic performance evaluation, biomedical ailment detection, and everyday fitness tracking. A test subject walked 20 steps on a flat surface at a comfortable speed wearing a shoe fitted with the insole and the main circuit board. Measurements were captured using a BLE enabled laptop and the test results were validated for accuracy. From the real-time data captured, the number of steps walked, the speed and the plantar pressure applied can be clearly established. Moreover, additional kinematic data from the motion sensor was captured. Further processing of kinematic data using techniques such as machine learning is essential to get meaningful inferences.
ContributorsBadarinath, Abhishek (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2018
Description
Modern-day automobiles are becoming more connected and reliant on wireless connectivity. Thus, automotive electronics can be both a cause of and highly sensitive to electromagnetic interference (EMI), and the consequences of failure can be fatal. Technology advancements in engineering have brought several features into the automotive field but at the expense of electromagnetic compatibility issues. Automotive EMC problems are the result of the emissions from electronic assemblies inside a vehicle and the susceptibility of the electronics when exposed to external EMI sources. In both cases, automotive EMC problems can cause unintended changes in the automotive system operation. Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state-of-the-art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this dissertation an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via the substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle, and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.
ContributorsRay, Abhishek (Author) / Bakkaloglu, Bertan (Thesis advisor) / Garrity, Douglas (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2023
Description
Handheld devices and personal laptops are becoming compact and complex every year with a demand to have higher power density, efficiency, and fast transient response. DC-DC boost converters are used in display and haptic drivers where the output voltage needs to be boosted higher than input voltage. The load transient response and unity gain bandwidth (UGB) of DC-DC boost converters are restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. The fast feedback (FFB) path is designed to achieve low output voltage change and fast settling time with the same UGB when compared to the conventional peak current mode control (CPCM). In the proposed PFFC method, the closed loop output impedance (ZOCL) is improved by reducing the DC value and by increasing the bandwidth of ZOCL as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for VOUT=5V, VIN=2.5V-4.4V and ILOAD=10mA-1A operating at a frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by ~2.6X and the undershoot reduces by 62% to 12μs and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/μs. The PFFC approach improves the settling time by 12X to 26us and reduces the overshoot by 56% to 56mV when compared to CPCM for 1A to 10mA load step at 2A/μs. The converter achieves a peak efficiency of 95.2% at 0.5W output power with VIN=4.4V and load regulation of 9mV/A at VIN=2.5V. The line transient response at VOUT=5V, ILOAD=700mA for VIN=3V ↔ 4V which is repeated at 280μs time period is 235mV and 245mV for CPCM and PFFC respectively.
ContributorsAlevoor, Shashank (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Sanyal, Arindham (Committee member) / Beohar, Navankur (Committee member) / Arizona State University (Publisher)
Created2023
Description
Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.
ContributorsVenkatasubramanian, Ramachandran (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Kitchen, Jennifer (Committee member) / Arizona State University (Publisher)
Created2016
Description
A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-
put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.
ContributorsMahmoudidaryan, Parisa (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Mehdizad Taleie, Shahin (Committee member) / Arizona State University (Publisher)
Created2019
Description
Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.
The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.
ContributorsSingh, Shrikant (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2019