ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 89
Description
This thesis addresses the issue of making an economic case for energy storage in power systems. Bulk energy storage has often been suggested for large scale electric power systems in order to levelize load; store energy when it is inexpensive and discharge energy when it is expensive; potentially defer transmission and generation expansion; and provide for generation reserve margins. As renewable energy resource penetration increases, the uncertainty and variability of wind and solar may be alleviated by bulk energy storage technologies. The quadratic programming function in MATLAB is used to simulate an economic dispatch that includes energy storage. A program is created that utilizes quadratic programming to analyze various cases using a 2010 summer peak load from the Arizona transmission system, part of the Western Electricity Coordinating Council (WECC). The MATLAB program is used first to test the Arizona test bed with a low level of energy storage to study how the storage power limit effects several optimization out-puts such as the system wide operating costs. Very high levels of energy storage are then added to see how high level energy storage affects peak shaving, load factor, and other system applications. Finally, various constraint relaxations are made to analyze why the applications tested eventually approach a constant value. This research illustrates the use of energy storage which helps minimize the system wide generator operating cost by "shaving" energy off of the peak demand.
ContributorsRuggiero, John (Author) / Heydt, Gerald T (Thesis advisor) / Datta, Rajib (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2013
Description
Underground cables have been widely used in big cities. This is because underground cables offer the benefits of reducing visual impact and the disturbance caused by bad weather (wind, ice, snow, and the lightning strikes). Additionally, when placing power lines underground, the maintenance costs can also be reduced as a result. The underground cable rating calculation is the most critical part of designing the cable construction and cable installation. In this thesis, three contributions regarding the cable ampacity study have been made. First, an analytical method for rating of underground cables has been presented. Second, this research also develops the steady state and transient ratings for Salt River Project (SRP) 69 kV underground system using the commercial software CYMCAP for several typical substations. Third, to find an alternative way to predict the cable ratings, three regression models have been built. The residual plot and mean square error for the three methods have been analyzed. The conclusion is dawn that the nonlinear regression model provides the sufficient accuracy of the cable rating prediction for SRP's typical installation.
ContributorsWang, Tong (Author) / Tylavsky, Daniel (Thesis advisor) / Karady, George G. (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis concerns the flashover issue of the substation insulators operating in a polluted environment. The outdoor insulation equipment used in the power delivery infrastructure encounter different types of pollutants due to varied environmental conditions. Various methods have been developed by manufacturers and researchers to mitigate the flashover problem. The application of Room Temperature Vulcanized (RTV) silicone rubber is one such favorable method as it can be applied over the already installed units. Field experience has already showed that the RTV silicone rubber coated insulators have a lower flashover probability than the uncoated insulators. The scope of this research is to quantify the improvement in the flashover performance. Artificial contamination tests were carried on station post insulators for assessing their performance. A factorial experiment design was used to model the flashover performance. The formulation included the severity of contamination and leakage distance of the insulator samples. Regression analysis was used to develop a mathematical model from the data obtained from the experiments. The main conclusion drawn from the study is that the RTV coated insulators withstood much higher levels of contamination even when the coating had lost its hydrophobicity. This improvement in flashover performance was found to be in the range of 20-40%. A much better flashover performance was observed when the coating recovered its hydrophobicity. It was also seen that the adhesion of coating was excellent even after many tests which involved substantial discharge activity.
ContributorsGholap, Vipul (Author) / Gorur, Ravi S (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
Renewable portfolio standards prescribe for penetration of high amounts of re-newable energy sources (RES) that may change the structure of existing power systems. The load growth and changes in power flow caused by RES integration may result in re-quirements of new available transmission capabilities and upgrades of existing transmis-sion paths. Construction difficulties of new transmission lines can become a problem in certain locations. The increase of transmission line thermal ratings by reconductoring using High Temperature Low Sag (HTLS) conductors is a comparatively new technology introduced to transmission expansion. A special design permits HTLS conductors to operate at high temperatures (e.g., 200oC), thereby allowing passage of higher current. The higher temperature capability increases the steady state and emergency thermal ratings of the transmission line. The main disadvantage of HTLS technology is high cost. The high cost may place special emphasis on a thorough analysis of cost to benefit of HTLS technology im-plementation. Increased transmission losses in HTLS conductors due to higher current may be a disadvantage that can reduce the attractiveness of this method. Studies described in this thesis evaluate the expenditures for transmission line re-conductoring using HTLS and the consequent benefits obtained from the potential decrease in operating cost for thermally limited transmission systems. Studies performed consider the load growth and penetration of distributed renewable energy sources according to the renewable portfolio standards for power systems. An evaluation of payback period is suggested to assess the cost to benefit ratio of HTLS upgrades. The thesis also considers the probabilistic nature of transmission upgrades. The well-known Chebyshev inequality is discussed with an application to transmission up-grades. The Chebyshev inequality is proposed to calculate minimum payback period ob-tained from the upgrades of certain transmission lines. The cost to benefit evaluation of HTLS upgrades is performed using a 225 bus equivalent of the 2012 summer peak Arizona portion of the Western Electricity Coordi-nating Council (WECC).
ContributorsTokombayev, Askhat (Author) / Heydt, Gerald T. (Thesis advisor) / Sankar, Lalitha (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2014
Description
The future grid will face challenges to meet an increased power demand by the consumers. Various solutions were studied to address this issue. One alternative to realize increased power flow in the grid is to use High Temperature Low Sag (HTLS) since it fulfills essential criteria of less sag and good material performance with temperature. HTLS conductors like Aluminum Conductor Composite Reinforced (ACCR) and Aluminum Conductor Carbon Composite (ACCC) are expected to face high operating temperatures of 150-200 degree Celsius in order to achieve the desired increased power flow. Therefore, it is imperative to characterize the material performance of these conductors with temperature. The work presented in this thesis addresses the characterization of carbon composite core based and metal matrix core based HTLS conductors. The thesis focuses on the study of variation of tensile strength of the carbon composite core with temperature and the level of temperature rise of the HTLS conductors due to fault currents cleared by backup protection. In this thesis, Dynamic Mechanical Analysis (DMA) was used to quantify the loss in storage modulus of carbon composite cores with temperature. It has been previously shown in literature that storage modulus is correlated to the tensile strength of the composite. Current temperature relationships of HTLS conductors were determined using the IEEE 738-2006 standard. Temperature rise of these conductors due to fault currents were also simulated. All simulations were performed using Microsoft Visual C++ suite. Tensile testing of metal matrix core was also performed. Results of DMA on carbon composite cores show that the storage modulus, hence tensile strength, decreases rapidly in the temperature range of intended use. DMA on composite cores subjected to heat treatment were conducted to investigate any changes in the variation of storage modulus curves. The experiments also indicates that carbon composites cores subjected to temperatures at or above 250 degree Celsius can cause permanent loss of mechanical properties including tensile strength. The fault current temperature analysis of carbon composite based conductors reveal that fault currents eventually cleared by backup protection in the event of primary protection failure can cause damage to fiber matrix interface.
ContributorsBanerjee, Koustubh (Author) / Gorur, Ravi (Committee member) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2014
Description
To uncover the neural correlates to go-directed behavior, single unit action potentials are considered fundamental computing units and have been examined by different analytical methodologies under a broad set of hypotheses. Using a behaving rat performing a directional choice learning task, we aim to study changes in rat's cortical neural patterns while he improved his task performance accuracy from chance to 80% or higher. Specifically, simultaneous multi-channel single unit neural recordings from the rat's agranular medial (AGm) and Agranular lateral (AGl) cortices were analyzed using joint peristimulus time histogram (JPSTHs), which effectively unveils firing coincidences in neural action potentials. My results based on data from six rats revealed that coincidences of pair-wise neural action potentials are higher when rats were performing the task than they were not at the learning stage, and this trend abated after the rats learned the task. Another finding is that the coincidences at the learning stage are stronger than that when the rats learned the task especially when they were performing the task. Therefore, this coincidence measure is the highest when the rats were performing the task at the learning stage. This may suggest that neural coincidences play a role in the coordination and communication among populations of neurons engaged in a purposeful act. Additionally, attention and working memory may have contributed to the modulation of neural coincidences during the designed task.
ContributorsCheng, Bing (Author) / Si, Jennie (Thesis advisor) / Chae, Junseok (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
A new photovoltaic (PV) array power converter circuit is presented. The salient features of this inverter are: transformerless topology, grounded PV array, and only film capacitors. The motivations are to reduce cost, eliminate leakage ground currents, and improve reliability. The use of Silicon Carbide (SiC) transistors is the key enabling technology for this particular circuit to attain good efficiency.
Traditionally, grid connected PV inverters required a transformer for isolation and safety. The disadvantage of high frequency transformer based inverters is complexity and cost. Transformerless inverters have become more popular recently, although they can be challenging to implement because of possible high frequency currents through the PV array's stay capacitance to earth ground. Conventional PV inverters also typically utilize electrolytic capacitors for bulk power buffering. However such capacitors can be prone to decreased reliability.
The solution proposed here to solve these problems is a bi directional buck boost converter combined with half bridge inverters. This configuration enables grounding of the array's negative terminal and passive power decoupling with only film capacitors.
Several aspects of the proposed converter are discussed. First a literature review is presented on the issues to be addressed. The proposed circuit is then presented and examined in detail. This includes theory of operation, component selection, and control systems. An efficiency analysis is also conducted. Simulation results are then presented that show correct functionality. A hardware prototype is built and experiment results also prove the concept. Finally some further developments are mentioned.
As a summary of the research a new topology and control technique were developed. The resultant circuit is a high performance transformerless PV inverter with upwards of 97% efficiency.
Traditionally, grid connected PV inverters required a transformer for isolation and safety. The disadvantage of high frequency transformer based inverters is complexity and cost. Transformerless inverters have become more popular recently, although they can be challenging to implement because of possible high frequency currents through the PV array's stay capacitance to earth ground. Conventional PV inverters also typically utilize electrolytic capacitors for bulk power buffering. However such capacitors can be prone to decreased reliability.
The solution proposed here to solve these problems is a bi directional buck boost converter combined with half bridge inverters. This configuration enables grounding of the array's negative terminal and passive power decoupling with only film capacitors.
Several aspects of the proposed converter are discussed. First a literature review is presented on the issues to be addressed. The proposed circuit is then presented and examined in detail. This includes theory of operation, component selection, and control systems. An efficiency analysis is also conducted. Simulation results are then presented that show correct functionality. A hardware prototype is built and experiment results also prove the concept. Finally some further developments are mentioned.
As a summary of the research a new topology and control technique were developed. The resultant circuit is a high performance transformerless PV inverter with upwards of 97% efficiency.
ContributorsBreazeale, Lloyd C (Author) / Ayyanar, Raja (Thesis advisor) / Karady, George G. (Committee member) / Tylavsky, Daniel (Committee member) / Tsakalis, Konstantinos (Committee member) / Arizona State University (Publisher)
Created2014
Description
Photovoltaic (PV) systems are affected by converter losses, partial shading and other mismatches in the panels. This dissertation introduces a sub-panel maximum power point tracking (MPPT) architecture together with an integrated CMOS current sensor circuit on a chip to reduce the mismatch effects, losses and increase the efficiency of the PV system. The sub-panel MPPT increases the efficiency of the PV during the shading and replaces the bypass diodes in the panels with an integrated MPPT and DC-DC regulator. For the integrated MPPT and regulator, the research developed an integrated standard CMOS low power and high common mode range Current-to-Digital Converter (IDC) circuit and its application for DC-DC regulator and MPPT. The proposed charge based CMOS switched-capacitor circuit directly digitizes the output current of the DC-DC regulator without an analog-to-digital converter (ADC) and the need for high-voltage process technology. Compared to the resistor based current-sensing methods that requires current-to-voltage circuit, gain block and ADC, the proposed CMOS IDC is a low-power efficient integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 0.7 um CMOS process, occupies 2mm x 2mm and consumes less than 27mW. The IDC circuit has been tested and used for boost DC-DC regulator and MPPT for photo-voltaic system. The DC-DC converter has an efficiency of 95%. The sub-module level power optimization improves the output power of a shaded panel by up to 20%, compared to panel MPPT with bypass diodes.
ContributorsMarti-Arbona, Edgar (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
t temperature (HST) and top-oil temperature (TOT) are reliable indicators of the insulation temperature. The objective of this project is to use thermal models to estimate the transformer's maximum dynamic loading capacity without violating the HST and TOT thermal limits set by the operator. In order to ensure the optimal loading, the temperature predictions of the thermal models need to be accurate. A number of transformer thermal models are available in the literature. In present practice, the IEEE Clause 7 model is used by the industry to make these predictions. However, a linear regression based thermal model has been observed to be more accurate than the IEEE model. These two models have been studied in this work.
This document presents the research conducted to discriminate between reliable and unreliable models with the help of certain metrics. This was done by first eyeballing the prediction performance and then evaluating a number of mathematical metrics. Efforts were made to recognize the cause behind an unreliable model. Also research was conducted to improve the accuracy of the performance of the existing models.
A new application, described in this document, has been developed to automate the process of building thermal models for multiple transformers. These thermal models can then be used for transformer dynamic loading.
This document presents the research conducted to discriminate between reliable and unreliable models with the help of certain metrics. This was done by first eyeballing the prediction performance and then evaluating a number of mathematical metrics. Efforts were made to recognize the cause behind an unreliable model. Also research was conducted to improve the accuracy of the performance of the existing models.
A new application, described in this document, has been developed to automate the process of building thermal models for multiple transformers. These thermal models can then be used for transformer dynamic loading.
ContributorsRao, Shruti Dwarkanath (Author) / Tylavsky, Daniel J (Thesis advisor) / Holbert, Keith E. (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2014
Description
This work describes the development of automated flows to generate pad rings, mixed signal power grids, and mega cells in a multi-project test chip. There were three major design flows that were created to create the test chip. The first was the pad ring which was used as the staring block for creating the test chip. This flow put all of the signals for the chip in the order that was wanted along the outside of the die along with creation of the power ring that is used to supply the chip with a robust power source.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
ContributorsLieb, Christopher (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2015