ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 41 - 45 of 45
Description
To keep up with the increasing demand for solar energy, higher efficiencies are necessary while keeping cost at a minimum. The easiest theoretical way to achieve that is using silicon-based multi-junction solar cells. However, there are major challenges in effectively implementing such a system. Much work has been done recently to integrate III-V with Si for multi-junction solar cell purposes. The focus of this paper is to explore GaP-based dilute nitrides as a possible top cell candidate for Si-based multi-junctions. The direct growth of dilute nitrides in a lattice-matched configuration epitaxially in literature is reviewed. The problems associated with such growths are outlined and pathways to mitigate these problems are presented. The need for a GaP buffer layer between the dilute nitride film and Si is established. Defects in GaP/Si system are explored in detail and a study on pit formation during such growth is performed. Effective suppression of pits in GaP surface grown on Si is achieved. Issues facing GaP-based dilute nitrides in terms of material properties are outlined. Review of these challenges is done and some possible future areas of interest to improve material quality are established. Finally, the growth process of dilute nitrides using Molecular Beam Epitaxy tool is explained. Results for GaNP grown on Si pre and post growth treatments are detailed.
ContributorsMurali, Srinath (Author) / Honsberg, Christiana (Thesis advisor) / Goodnick, Stephen (Committee member) / King, Richard (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022
Description
The research of alternative materials and new device architectures to exceed the limits of conventional silicon-based devices has been sparked by the persistent pursuit of semiconductor technology scaling. The development of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), well-known member of the transition metal dichalcogenide (TMD) family, has made great strides towards ultrascaled two-dimensional (2D) field-effect-transistors (FETs). The scaling issues facing silicon-based complementary metal-oxide-semiconductor (CMOS) technologies can be solved by 2D FETs, which show extraordinary potential.This dissertation provides a comprehensive experimental analysis relating to improvements in p-type metal-oxide-semiconductor (PMOS) FETs with few-layer WSe2 and high-κ metal gate (HKMG) stacks. Compared to this works improved methods, standard metallization (more damaging to underlying channel) results in significant Fermi-level pinning, although Schottky barrier heights remain small (< 100 meV) when using high work function metals. Temperature-dependent analysis reveals a dominant contribution to contact resistance from the damaged channel access region. Thus, through less damaging metallization methods combined with strongly scaled HKMG stacks significant improvements were achieved in contact resistance and PMOS FET overall performance. A clean contact/channel interface was achieved through high-vacuum evaporation and temperature-controlled stepped deposition. Theoretical analysis using a Landauer transport adapted to WSe2 Schottky barrier FETs (SB-FETs) elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance towards the ultimate CMOS scaling limit.
Next, this dissertation discusses how device electrical characteristics are affected by scaling of equivalent oxide thickness (EOT) and by adopting double-gate FET architectures, as well as how this might support CMOS scaling. An improved gate control over the channel is made possible by scaling EOT, improving on-off current ratios, carrier mobility, and subthreshold swing. This study also elucidates the impact of EOT scaling on FET gate hysteresis attributed to charge-trapping effects in high-κ-dielectrics prepared by atomic layer deposition (ALD). These developments in 2D FETs offer a compelling alternative to conventional silicon-based devices and a path for continued transistor scaling. This research contributes to ongoing efforts in 2D materials for future semiconductor technologies. Finally, this work introduces devices based on emerging Janus TMDs and bismuth oxyselenide (Bi2O2Se) layered semiconductors.
ContributorsPatoary, Md Naim Hossain (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Tongay, Sefaattin (Committee member) / Vasileska, Dragica (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2023
Description
This study focuses on the implications of a high reverse bias breakdown in silicon heterojunction cells (SHJ). In relevant literature, there is a lack of explicit investigation which
compares high breakdown voltage cells (commonly SHJ) to low breakdown voltage cells
(commonly silicon homojunctions) in an installation setting. In addition, their relationship with
shading and how they react with bypass diodes are also not very prevalent. Therefore, my project
dives into how shading impacts a string of high breakdown voltage cells and a string of low
breakdown voltage cells, as well as how those cells interact with a bypass diode.
In order to conduct this investigation, I used the simulation software LTSpice XVII to
create an accurate simulation model of a SHJ cell with a 21 V reverse breakdown voltage. With
this cell model, I strung 10 cells together, and varied the shading on a single cell while measuring
the string’s output current, voltage, and power. Next, I attached a bypass diode to the shaded
cell, and continued to increase the number of cells attached to the bypass diode while continuing
to examine the string’s output. Once I gathered this data, I modified the original cell model to
have a lower reverse breakdown voltage of 5 V. From here, I strung 10 cells together again, and
repeated the same measurements from the 21 V string.
Upon completing these measurements, I found that the SHJ cells were in fact harder to
force into reverse bias than the cells with the lower reverse breakdown voltage, suggesting that
solar installation owners should consider transitioning to SHJ-based modules. When bypass
diodes are being considered, my results demonstrated that heavy shading (about 65% and
higher) was required for the bypass diodes to have an observable impact on the string’s power
output. Therefore, owners should consider how severe the shading their installation may receive
before investing in bypass diodes. If owners do find the need for the bypass diodes, my findings
also show that the diodes should be used sparingly and in a compromise with output power and
cost.
ContributorsAvalos, Christian (Author) / Honsberg, Christiana (Thesis advisor) / Bowden, Stuart (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2023
Description
Scaling of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) towards shorter channel lengths, has lead to an increasing importance of quantum effects on the device performance. Until now, a semi-classical model based on Monte Carlo method for instance, has been sufficient to address these issues in silicon, and arrive at a reasonably good fit to experimental mobility data. But as the semiconductor world moves towards 10nm technology, many of the basic assumptions in this method, namely the very fundamental Fermi’s golden rule come into question. The derivation of the Fermi’s golden rule assumes that the scattering is infrequent (therefore the long time limit) and the collision duration time is zero. This thesis overcomes some of the limitations of the above approach by successfully developing a quantum mechanical simulator that can model the low-field inversion layer mobility in silicon MOS capacitors and other inversion layers as well. It solves for the scattering induced collisional broadening of the states by accounting for the various scattering mechanisms present in silicon through the non-equilibrium based near-equilibrium Green’s Functions approach, which shall be referred to as near-equilibrium Green’s Function (nEGF) in this work. It adopts a two-loop approach, where the outer loop solves for the self-consistency between the potential and the subband sheet charge density by solving the Poisson and the Schrödinger equations self-consistently. The inner loop solves for the nEGF (renormalization of the spectrum and the broadening of the states), self-consistently using the self-consistent Born approximation, which is then used to compute the mobility using the Green-Kubo Formalism.
ContributorsJayaram Thulasingam, Gokula Kannan (Author) / Vasileska, Dragica (Thesis advisor) / Ferry, David (Committee member) / Goodnick, Stephen (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2017
Description
An efficient thermal solver is available in the CMC that allows modeling self-heating in the electrical simulations, which treats phonons as flux and solves the energy balance equation to quantify thermal effects. Using this solver, thermal simulations were performed on GaN-HEMTs in order to test effect of gate architectures on the DC and RF performance of the device. A Π- gate geometry is found to suppress 19.75% more hot electrons corresponding to a DC power of 2.493 W/mm for Vgs = -0.6V (max transconductance) with respect to the initial T-gate. For the DC performance, the output current, Ids is nearly same for each device configuration over the entire bias range. For the RF performance, the current gain was evaluated over a frequency range 20 GHz to 120 GHz in each device for both thermal (including self-heating) and isothermal (without self-heating). The evaluated cutoff frequency is around 7% lower for the thermal case than the isothermal case. The simulated cutoff frequency closely follows the experimental cutoff frequency. The work was extended to the study of ultra-wide bandgap material (Diamond), where isotope effect causes major deterioration in thermal conductivity. In this case, bulk phonons are modeled as semiclassical particles solving the nonlinear Peierls - Boltzmann transport equation with a stochastic approach. Simulations were performed for 0.001% (ultra-pure), 0.1% and 1.07% isotope concentration (13C) of diamond, showing good agreement with the experimental values. Further investigation was performed on the effect of isotope on the dynamics of individual phonon branches, thermal conductivity and the mean free path, to identify the dominant phonon branch. Acoustic phonons are found to be the principal contributors to thermal conductivity across all isotope concentrations with transverse acoustic (TA2) branch is the dominant branch with a contribution of 40% at room temperature and 37% at 500K. Mean free path computations show the lower bound of device dimensions in order to obtain maximum thermal conductivity. At 300K, the lowest mean free path (which is attributed to Longitudinal Optical phonon) reduces from 24nm to 8 nm for isotope concentration of 0.001% and 1.07% respectively. Similarly, the maximum mean free path (which is attributed to Longitudinal Acoustic phonon) reduces from 4 µm to 3.1 µm, respectively, for the same isotope concentrations. Furthermore, PETSc (Portable, Extensible Toolkit for Scientific Computation) developed by Argonne National Lab, was included in the existing Cellular Monte Carlo device simulator as a Poisson solver to further extend the capability of the simulator. The validity of the solver was tested performing 2D and 3D simulations and the results were compared with the well-established multigrid Poisson solver.
ContributorsAcharjee, Joy (Author) / Saraniti, Marco (Thesis advisor) / Goodnick, Stephen (Committee member) / Thornton, Trevor (Committee member) / Wang, Robert (Committee member) / Arizona State University (Publisher)
Created2024