ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 74
Description
The repertoire of the saxophone has advanced significantly since its invention circa 1840. Performers are required to adapt to the demands of composers - many of whom are exploring new and unconventional sounds and techniques. Numerous texts exist to identify and explain these so-called "extended" techniques, but there are very few resources for the initial stages of performance. In order to offer performers a resource, the author of this text composed forty original etudes (or studies) that incorporate extended techniques in a variety of ways. After identifying common extended techniques that a performer might face, the author focused on four different ways each individual technique might appear in actual repertoire. The resulting work is entitled Pushing Boundaries: Forty Etudes on Extended Techniques. Each etude offers a practical approach to what is generally a single extended technique. Although this text is not pedagogical in the sense of identifying the mechanics and anatomical requirements of each technique, it does contain a performance analysis of each etude. This analysis identifies areas where performers might struggle and offers helpful suggestions. To this end, the etudes accompanied by performance analysis provide a paced, systematic approach to the mastery of each technique.
ContributorsMurphy, Patrick Joseph (Author) / Hill, Gary (Thesis advisor) / Spring, Robert (Committee member) / McAllister, Timothy (Committee member) / Micklich, Albie (Committee member) / DeMars, James (Committee member) / Arizona State University (Publisher)
Created2013
Description
CYOA is a prototype of an iPhone application that produces a single, generative, musical work. This document details some of the thoughts and practices that informed its design, and specifically addresses the overlap between application structure and musical form. The concept of composed instruments is introduced and briefly discussed, some features of video game design that relate to this project are considered, and some specifics of hardware implementation are addressed.
ContributorsPeterson, Julian (Author) / Hackbarth, Glenn (Thesis advisor) / DeMars, James (Committee member) / Feisst, Sabine (Committee member) / Levy, Benjamin (Committee member) / Tobias, Evan (Committee member) / Arizona State University (Publisher)
Created2013
Description
In recent years we have witnessed a shift towards multi-processor system-on-chips (MPSoCs) to address the demands of embedded devices (such as cell phones, GPS devices, luxury car features, etc.). Highly optimized MPSoCs are well-suited to tackle the complex application demands desired by the end user customer. These MPSoCs incorporate a constellation of heterogeneous processing elements (PEs) (general purpose PEs and application-specific integrated circuits (ASICS)). A typical MPSoC will be composed of a application processor, such as an ARM Coretex-A9 with cache coherent memory hierarchy, and several application sub-systems. Each of these sub-systems are composed of highly optimized instruction processors, graphics/DSP processors, and custom hardware accelerators. Typically, these sub-systems utilize scratchpad memories (SPM) rather than support cache coherency. The overall architecture is an integration of the various sub-systems through a high bandwidth system-level interconnect (such as a Network-on-Chip (NoC)). The shift to MPSoCs has been fueled by three major factors: demand for high performance, the use of component libraries, and short design turn around time. As customers continue to desire more and more complex applications on their embedded devices the performance demand for these devices continues to increase. Designers have turned to using MPSoCs to address this demand. By using pre-made IP libraries designers can quickly piece together a MPSoC that will meet the application demands of the end user with minimal time spent designing new hardware. Additionally, the use of MPSoCs allows designers to generate new devices very quickly and thus reducing the time to market. In this work, a complete MPSoC synthesis design flow is presented. We first present a technique \cite{leary1_intro} to address the synthesis of the interconnect architecture (particularly Network-on-Chip (NoC)). We then address the synthesis of the memory architecture of a MPSoC sub-system \cite{leary2_intro}. Lastly, we present a co-synthesis technique to generate the functional and memory architectures simultaneously. The validity and quality of each synthesis technique is demonstrated through extensive experimentation.
ContributorsLeary, Glenn (Author) / Chatha, Karamvir S (Thesis advisor) / Vrudhula, Sarma (Committee member) / Shrivastava, Aviral (Committee member) / Beraha, Rudy (Committee member) / Arizona State University (Publisher)
Created2013
Description
Three Meditations on the Philosophy of Boethius is a musical piece for guitar, piano interior, and computer. Each of the three movements, or meditations, reflects one level of music according to the medieval philosopher Boethius: Musica Mundana, Musica Humana, and Musica Instrumentalis. From spatial aspects, through the human element, to letting sound evolve freely, different movements revolve around different sounds and sound producing techniques.
ContributorsDori, Gil (Contributor) / Hackbarth, Glenn (Thesis advisor) / DeMars, James (Committee member) / Feisst, Sabine (Committee member) / Arizona State University (Publisher)
Created2013
Description
Piano Quintet> is a three movement piece, inspired by music of Eastern Europe. Sunrise in Hungary starts with a legato song in the first violin unfolding over slow moving sustained harmonics in the rest of the strings. This is contrasted with a lively Hungarian dance which starts in the piano and jumps throughout all of the voices. Armenian Lament introduces a mournful melody performed over a subtly shifting pedal tone in the cello. The rest of the voices are slowly introduced until the movement builds into a canonic threnody. Evening in Bulgaria borrows from the vast repertoire of Bulgarian dances, including rhythms from the horo and rachenitsa. Each time that the movement returns to the primary theme, it incorporates aspects of the dance that directly preceded it. The final return is the crux of the piece, with the first violin playing a virtuosic ornaments run on the melody.
ContributorsGiese, Adam (Composer) / Hackbarth, Glenn (Thesis advisor) / DeMars, James (Committee member) / Feisst, Sabine (Committee member) / Arizona State University (Publisher)
Created2014
Description
Concerto for Piano and Chamber Orchestra was conceived in February of 2013, and conceptually it is my attempt to fuse personal expressions of jazz and classical music into one fully realized statement. It is a three movement work (fast, slow, fast) for 2 fl., 2 ob., 2 cl., bsn., 2 hrn., 2 tpt., tbn., pno., perc., str. (6,4,2,2,1). The work is approximately 27 minutes in duration. The first movement of the Concerto is written in a fluid sonata form. A fugato begins where the second theme would normally appear, and the second theme does not fully appear until near the end of the solo piano section. The result is that the second theme when finally revealed is so reminiscent of the history of jazz and classical synthesis that it does not sound completely new, and in fact is a return of something that was heard before, but only hinted at in this piece. The second movement is a kind of deconstructive set of variations, with a specific theme and harmonic pattern implied throughout the movement. However, the full theme is not disclosed until the final variation. The variations are interrupted by moments of pure rhythmic music, containing harmony made up of major chords with an added fourth, defying resolution, and dissolving each time back into a new variation. The third movement is in rondo form, using rhythmic and harmonic influences from jazz. The percussion plays a substantial role in this movement, acting as a counterpoint to the piano part throughout. This movement and the piece concludes with an extended coda, inspired indirectly by the simple complexities of an improvisational piano solo, building in complexity as the concerto draws to a close.
ContributorsSneider, Elliot (Author) / Rogers, Rodney (Thesis advisor) / DeMars, James (Committee member) / Hackbarth, Glenn (Committee member) / Solis, Theodore (Committee member) / Arizona State University (Publisher)
Created2013
Description
In this thesis we deal with the problem of temporal logic robustness estimation. We present a dynamic programming algorithm for the robust estimation problem of Metric Temporal Logic (MTL) formulas regarding a finite trace of time stated sequence. This algorithm not only tests if the MTL specification is satisfied by the given input which is a finite system trajectory, but also quantifies to what extend does the sequence satisfies or violates the MTL specification. The implementation of the algorithm is the DP-TALIRO toolbox for MATLAB. Currently it is used as the temporal logic robust computing engine of S-TALIRO which is a tool for MATLAB searching for trajectories of minimal robustness in Simulink/ Stateflow. DP-TALIRO is expected to have near linear running time and constant memory requirement depending on the structure of the MTL formula. DP-TALIRO toolbox also integrates new features not supported in its ancestor FW-TALIRO such as parameter replacement, most related iteration and most related predicate. A derivative of DP-TALIRO which is DP-T-TALIRO is also addressed in this thesis which applies dynamic programming algorithm for time robustness computation. We test the running time of DP-TALIRO and compare it with FW-TALIRO. Finally, we present an application where DP-TALIRO is used as the robustness computation core of S-TALIRO for a parameter estimation problem.
ContributorsYang, Hengyi (Author) / Fainekos, Georgios (Thesis advisor) / Sarjoughian, Hessam S. (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2013
Description
Software has a great impact on the energy efficiency of any computing system--it can manage the components of a system efficiently or inefficiently. The impact of software is amplified in the context of a wearable computing system used for activity recognition. The design space this platform opens up is immense and encompasses sensors, feature calculations, activity classification algorithms, sleep schedules, and transmission protocols. Design choices in each of these areas impact energy use, overall accuracy, and usefulness of the system. This thesis explores methods software can influence the trade-off between energy consumption and system accuracy. In general the more energy a system consumes the more accurate will be. We explore how finding the transitions between human activities is able to reduce the energy consumption of such systems without reducing much accuracy. We introduce the Log-likelihood Ratio Test as a method to detect transitions, and explore how choices of sensor, feature calculations, and parameters concerning time segmentation affect the accuracy of this method. We discovered an approximate 5X increase in energy efficiency could be achieved with only a 5% decrease in accuracy. We also address how a system's sleep mode, in which the processor enters a low-power state and sensors are turned off, affects a wearable computing platform that does activity recognition. We discuss the energy trade-offs in each stage of the activity recognition process. We find that careful analysis of these parameters can result in great increases in energy efficiency if small compromises in overall accuracy can be tolerated. We call this the ``Great Compromise.'' We found a 6X increase in efficiency with a 7% decrease in accuracy. We then consider how wireless transmission of data affects the overall energy efficiency of a wearable computing platform. We find that design decisions such as feature calculations and grouping size have a great impact on the energy consumption of the system because of the amount of data that is stored and transmitted. For example, storing and transmitting vector-based features such as FFT or DCT do not compress the signal and would use more energy than storing and transmitting the raw signal. The effect of grouping size on energy consumption depends on the feature. For scalar features energy consumption is proportional in the inverse of grouping size, so it's reduced as grouping size goes up. For features that depend on the grouping size, such as FFT, energy increases with the logarithm of grouping size, so energy consumption increases slowly as grouping size increases. We find that compressing data through activity classification and transition detection significantly reduces energy consumption and that the energy consumed for the classification overhead is negligible compared to the energy savings from data compression. We provide mathematical models of energy usage and data generation, and test our ideas using a mobile computing platform, the Texas Instruments Chronos watch.
ContributorsBoyd, Jeffrey Michael (Author) / Sundaram, Hari (Thesis advisor) / Li, Baoxin (Thesis advisor) / Shrivastava, Aviral (Committee member) / Turaga, Pavan (Committee member) / Arizona State University (Publisher)
Created2014
Description
Preservation Symphony is a short, multi-movement, orchestral composition that explores the versatility of the [016] pitch class set as the dominant unifying force of this cyclical work. The composition is scored for Piccolo, two Flutes, two Oboes, English Horn, two Clarinets, Bass Clarinet, full complement of Brass, Timpani, two Percussionists, and Strings. Movement one is in sonata form; the [016] set is used in structuring its overall formal scheme. The primary focus of the movement is on the tritone [0 6] as a replacement for the traditional tonic and dominant polarity. The movement features a driving force that alternates between pulse subdivisions of even sixteenth notes and sixteenth-note triplets. Movement two is in simple binary form with a central tonality of A. An English Horn solo functions as both the opening of the movement and a transition from the tonality of movement one (F) into the new tonal center of A. The unifying pitch class set [016] is used in this movement in a Phrygian context. Movement two has a contemplative and dark tone, which is in stark contrast to the outer movements. Movement three has a lighter, upbeat nature. The movement is in rondo form with its main theme written in a folk-like character. This movement returns to F as the central tonality, completing the overall tonal plan of the work. As in movement one, it explores the tritone polarity of F and B. The movement also revisits the chromatic mediant relationship found in the middle of movement two in the oboes. The pitch class set is now used in the context of a Lydian-Mixolydian (or acoustic) scale, from which both the central and secondary themes of the rondo are derived.
ContributorsKemp, Tyler (Composer) / Rogers, Rodney (Thesis advisor) / DeMars, James (Committee member) / Rockmaker, Jody (Committee member) / Arizona State University (Publisher)
Created2014
Description
Stream processing has emerged as an important model of computation especially in the context of multimedia and communication sub-systems of embedded System-on-Chip (SoC) architectures. The dataflow nature of streaming applications allows them to be most naturally expressed as a set of kernels iteratively operating on continuous streams of data. The kernels are computationally intensive and are mainly characterized by real-time constraints that demand high throughput and data bandwidth with limited global data reuse. Conventional architectures fail to meet these demands due to their poorly matched execution models and the overheads associated with instruction and data movements.
This work presents StreamWorks, a multi-core embedded architecture for energy-efficient stream computing. The basic processing element in the StreamWorks architecture is the StreamEngine (SE) which is responsible for iteratively executing a stream kernel. SE introduces an instruction locking mechanism that exploits the iterative nature of the kernels and enables fine-grain instruction reuse. Each instruction in a SE is locked to a Reservation Station (RS) and revitalizes itself after execution; thus never retiring from the RS. The entire kernel is hosted in RS Banks (RSBs) close to functional units for energy-efficient instruction delivery. The dataflow semantics of stream kernels are captured by a context-aware dataflow execution mode that efficiently exploits the Instruction Level Parallelism (ILP) and Data-level parallelism (DLP) within stream kernels.
Multiple SEs are grouped together to form a StreamCluster (SC) that communicate via a local interconnect. A novel software FIFO virtualization technique with split-join functionality is proposed for efficient and scalable stream communication across SEs. The proposed communication mechanism exploits the Task-level parallelism (TLP) of the stream application. The performance and scalability of the communication mechanism is evaluated against the existing data movement schemes for scratchpad based multi-core architectures. Further, overlay schemes and architectural support are proposed that allow hosting any number of kernels on the StreamWorks architecture. The proposed oevrlay schemes for code management supports kernel(context) switching for the most common use cases and can be adapted for any multi-core architecture that use software managed local memories.
The performance and energy-efficiency of the StreamWorks architecture is evaluated for stream kernel and application benchmarks by implementing the architecture in 45nm TSMC and comparison with a low power RISC core and a contemporary accelerator.
This work presents StreamWorks, a multi-core embedded architecture for energy-efficient stream computing. The basic processing element in the StreamWorks architecture is the StreamEngine (SE) which is responsible for iteratively executing a stream kernel. SE introduces an instruction locking mechanism that exploits the iterative nature of the kernels and enables fine-grain instruction reuse. Each instruction in a SE is locked to a Reservation Station (RS) and revitalizes itself after execution; thus never retiring from the RS. The entire kernel is hosted in RS Banks (RSBs) close to functional units for energy-efficient instruction delivery. The dataflow semantics of stream kernels are captured by a context-aware dataflow execution mode that efficiently exploits the Instruction Level Parallelism (ILP) and Data-level parallelism (DLP) within stream kernels.
Multiple SEs are grouped together to form a StreamCluster (SC) that communicate via a local interconnect. A novel software FIFO virtualization technique with split-join functionality is proposed for efficient and scalable stream communication across SEs. The proposed communication mechanism exploits the Task-level parallelism (TLP) of the stream application. The performance and scalability of the communication mechanism is evaluated against the existing data movement schemes for scratchpad based multi-core architectures. Further, overlay schemes and architectural support are proposed that allow hosting any number of kernels on the StreamWorks architecture. The proposed oevrlay schemes for code management supports kernel(context) switching for the most common use cases and can be adapted for any multi-core architecture that use software managed local memories.
The performance and energy-efficiency of the StreamWorks architecture is evaluated for stream kernel and application benchmarks by implementing the architecture in 45nm TSMC and comparison with a low power RISC core and a contemporary accelerator.
ContributorsPanda, Amrit (Author) / Chatha, Karam S. (Thesis advisor) / Wu, Carole-Jean (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Shrivastava, Aviral (Committee member) / Arizona State University (Publisher)
Created2014