ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 78
Description
Topological insulators with conducting surface states yet insulating bulk states have generated a lot of interest amongst the physics community due to their varied characteristics and possible applications. Doped topological insulators have presented newer physical states of matter where topological order co&ndashexists; with other physical properties (like magnetic order). The electronic states of these materials are very intriguing and pose problems and the possible solutions to understanding their unique behaviors. In this work, we use Electron Energy Loss Spectroscopy (EELS) – an analytical TEM tool to study both core&ndashlevel; and valence&ndashlevel; excitations in Bi2Se3 and Cu(doped)Bi2Se3 topological insulators. We use this technique to retrieve information on the valence, bonding nature, co-ordination and lattice site occupancy of the undoped and the doped systems. Using the reference materials Cu(I)Se and Cu(II)Se we try to compare and understand the nature of doping that copper assumes in the lattice. And lastly we utilize the state of the art monochromated Nion UltraSTEM 100 to study electronic/vibrational excitations at a record energy resolution from sub-nm regions in the sample.
ContributorsSubramanian, Ganesh (Author) / Spence, John (Thesis advisor) / Jiang, Nan (Committee member) / Chen, Tingyong (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2013
Description
Dealloying, the selective dissolution of an elemental component from an alloy, is an important corrosion mechanism and a technological significant means to fabricate nanoporous structures for a variety of applications. In noble metal alloys, dealloying proceeds above a composition dependent critical potential, and bi-continuous structure evolves "simultaneously" as a result of the interplay between percolation dissolution and surface diffusion. In contrast, dealloying in alloys that show considerable solid-state mass transport at ambient temperature is largely unexplored despite its relevance to nanoparticle catalysts and Li-ion anodes. In my dissertation, I discuss the behaviors of two alloy systems in order to elucidate the role of bulk lattice diffusion in dealloying. First, Mg-Cd alloys are chosen to show that when the dealloying is controlled by bulk diffusion, a new type of porosity - negative void dendrites will form, and the process mirrors electrodeposition. Then, Li-Sn alloys are studied with respect to the composition, particle size and dealloying rate effects on the morphology evolution. Under the right condition, dealloying of Li-Sn supported by percolation dissolution results in the same bi-continuous structure as nanoporous noble metals; whereas lattice diffusion through the otherwise "passivated" surface allows for dealloying with no porosity evolution. The interactions between bulk diffusion, surface diffusion and dissolution are revealed by chronopotentiometry and linear sweep voltammetry technics. The better understanding of dealloying from these experiments enables me to construct a brief review summarizing the electrochemistry and morphology aspects of dealloying as well as offering interpretations to new observations such as critical size effect and encased voids in nanoporous gold. At the end of the dissertation, I will describe a preliminary attempt to generalize the morphology evolution "rules of dealloying" to all solid-to-solid interfacial controlled phase transition process, demonstrating that bi-continuous morphologies can evolve regardless of the nature of parent phase.
ContributorsChen, Qing (Author) / Sieradzki, Karl (Thesis advisor) / Friesen, Cody (Committee member) / Buttry, Daniel (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2013
Description
To uncover the neural correlates to go-directed behavior, single unit action potentials are considered fundamental computing units and have been examined by different analytical methodologies under a broad set of hypotheses. Using a behaving rat performing a directional choice learning task, we aim to study changes in rat's cortical neural patterns while he improved his task performance accuracy from chance to 80% or higher. Specifically, simultaneous multi-channel single unit neural recordings from the rat's agranular medial (AGm) and Agranular lateral (AGl) cortices were analyzed using joint peristimulus time histogram (JPSTHs), which effectively unveils firing coincidences in neural action potentials. My results based on data from six rats revealed that coincidences of pair-wise neural action potentials are higher when rats were performing the task than they were not at the learning stage, and this trend abated after the rats learned the task. Another finding is that the coincidences at the learning stage are stronger than that when the rats learned the task especially when they were performing the task. Therefore, this coincidence measure is the highest when the rats were performing the task at the learning stage. This may suggest that neural coincidences play a role in the coordination and communication among populations of neurons engaged in a purposeful act. Additionally, attention and working memory may have contributed to the modulation of neural coincidences during the designed task.
ContributorsCheng, Bing (Author) / Si, Jennie (Thesis advisor) / Chae, Junseok (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
Photovoltaic (PV) systems are affected by converter losses, partial shading and other mismatches in the panels. This dissertation introduces a sub-panel maximum power point tracking (MPPT) architecture together with an integrated CMOS current sensor circuit on a chip to reduce the mismatch effects, losses and increase the efficiency of the PV system. The sub-panel MPPT increases the efficiency of the PV during the shading and replaces the bypass diodes in the panels with an integrated MPPT and DC-DC regulator. For the integrated MPPT and regulator, the research developed an integrated standard CMOS low power and high common mode range Current-to-Digital Converter (IDC) circuit and its application for DC-DC regulator and MPPT. The proposed charge based CMOS switched-capacitor circuit directly digitizes the output current of the DC-DC regulator without an analog-to-digital converter (ADC) and the need for high-voltage process technology. Compared to the resistor based current-sensing methods that requires current-to-voltage circuit, gain block and ADC, the proposed CMOS IDC is a low-power efficient integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 0.7 um CMOS process, occupies 2mm x 2mm and consumes less than 27mW. The IDC circuit has been tested and used for boost DC-DC regulator and MPPT for photo-voltaic system. The DC-DC converter has an efficiency of 95%. The sub-module level power optimization improves the output power of a shaded panel by up to 20%, compared to panel MPPT with bypass diodes.
ContributorsMarti-Arbona, Edgar (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Kitchen, Jennifer (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
This work describes the development of automated flows to generate pad rings, mixed signal power grids, and mega cells in a multi-project test chip. There were three major design flows that were created to create the test chip. The first was the pad ring which was used as the staring block for creating the test chip. This flow put all of the signals for the chip in the order that was wanted along the outside of the die along with creation of the power ring that is used to supply the chip with a robust power source.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
The second flow that was created was used to put together a flash block that is based off of a XILIX XCFXXP. This flow was somewhat similar to how the pad ring flow worked except that optimizations and a clock tree was added into the flow. There was a couple of design redoes due to timing and orientation constraints.
Finally, the last flow that was created was the top level flow which is where all of the components are combined together to create a finished test chip ready for fabrication. The main components that were used were the finished flash block, HERMES, test structures, and a clock instance along with the pad ring flow for the creation of the pad ring and power ring.
Also discussed is some work that was done on a previous multi-project test chip. The work that was done was the creation of power gaters that were used like switches to turn the power on and off for some flash modules. To control the power gaters the functionality change of some pad drivers was done so that they output a higher voltage than what is seen in the core of the chip.
ContributorsLieb, Christopher (Author) / Clark, Lawrence (Thesis advisor) / Holbert, Keith E. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2015
Description
Switching Converters (SC) are an excellent choice for hand held devices due to their high power conversion efficiency. However, they suffer from two major drawbacks. The first drawback is that their dynamic response is sensitive to variations in inductor (L) and capacitor (C) values. A cost effective solution is implemented by designing a programmable digital controller. Despite variations in L and C values, the target dynamic response can be achieved by computing and programming the filter coefficients for a particular L and C. Besides, digital controllers have higher immunity to environmental changes such as temperature and aging of components. The second drawback of SCs is their poor efficiency during low load conditions if operated in Pulse Width Modulation (PWM) mode. However, if operated in Pulse Frequency Modulation (PFM) mode, better efficiency numbers can be achieved. A mostly-digital way of detecting PFM mode is implemented. Besides, a slow serial interface to program the chip, and a high speed serial interface to characterize mixed signal blocks as well as to ship data in or out for debug purposes are designed. The chip is taped out in 0.18µm IBM's radiation hardened CMOS process technology. A test board is built with the chip, external power FETs and driver IC. At the time of this writing, PWM operation, PFM detection, transitions between PWM and PFM, and both serial interfaces are validated on the test board.
ContributorsMumma Reddy, Abhiram (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ogras, Umit Y. (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2014
Description
Membrane-based gas separation is promising for efficient propylene/propane (C3H6/C3H8) separation with low energy consumption and minimum environment impact. Two microporous inorganic membrane candidates, MFI-type zeolite membrane and carbon molecular sieve membrane (CMS) have demonstrated excellent thermal and chemical stability. Application of these membranes into C3H6/C3H8 separation has not been well investigated. This dissertation presents fundamental studies on membrane synthesis, characterization and C3H6/C3H8 separation properties of MFI zeolite membrane and CMS membrane.
MFI zeolite membranes were synthesized on α-alumina supports by secondary growth method. Novel positron annihilation spectroscopy (PAS) techniques were used to non-destructively characterize the pore structure of these membranes. PAS reveals a bimodal pore structure consisting of intracrystalline zeolitic micropores of ~0.6 nm in diameter and irregular intercrystalline micropores of 1.4 to 1.8 nm in size for the membranes. The template-free synthesized membrane exhibited a high permeance but a low selectivity in C3H6/C3H8 mixture separation.
CMS membranes were synthesized by coating/pyrolysis method on mesoporous γ-alumina support. Such supports allow coating of thin, high-quality polymer films and subsequent CMS membranes with no infiltration into support pores. The CMS membranes show strong molecular sieving effect, offering a high C3H6/C3H8 mixture selectivity of ~30. Reduction in membrane thickness from 500 nm to 300 nm causes an increase in C3H8 permeance and He/N2 selectivity, but a decrease in the permeance of He, N2 and C3H6 and C3H6/C3H8 selectivity. This can be explained by the thickness dependent chain mobility of the polymer film resulting in final carbon membrane of reduced pore size with different effects on transport of gas of different sizes, including possible closure of C3H6-accessible micropores.
CMS membranes demonstrate excellent C3H6/C3H8 separation performance over a wide range of feed pressure, composition and operation temperature. No plasticization was observed at a feed pressure up to 100 psi. The permeation and separation is mainly controlled by diffusion instead of adsorption. CMS membrane experienced a decline in permeance, and an increase in selectivity over time under on-stream C3H6/C3H8 separation. This aging behavior is due to the reduction in effective pore size and porosity caused by oxygen chemisorption and physical aging of the membrane structure.
MFI zeolite membranes were synthesized on α-alumina supports by secondary growth method. Novel positron annihilation spectroscopy (PAS) techniques were used to non-destructively characterize the pore structure of these membranes. PAS reveals a bimodal pore structure consisting of intracrystalline zeolitic micropores of ~0.6 nm in diameter and irregular intercrystalline micropores of 1.4 to 1.8 nm in size for the membranes. The template-free synthesized membrane exhibited a high permeance but a low selectivity in C3H6/C3H8 mixture separation.
CMS membranes were synthesized by coating/pyrolysis method on mesoporous γ-alumina support. Such supports allow coating of thin, high-quality polymer films and subsequent CMS membranes with no infiltration into support pores. The CMS membranes show strong molecular sieving effect, offering a high C3H6/C3H8 mixture selectivity of ~30. Reduction in membrane thickness from 500 nm to 300 nm causes an increase in C3H8 permeance and He/N2 selectivity, but a decrease in the permeance of He, N2 and C3H6 and C3H6/C3H8 selectivity. This can be explained by the thickness dependent chain mobility of the polymer film resulting in final carbon membrane of reduced pore size with different effects on transport of gas of different sizes, including possible closure of C3H6-accessible micropores.
CMS membranes demonstrate excellent C3H6/C3H8 separation performance over a wide range of feed pressure, composition and operation temperature. No plasticization was observed at a feed pressure up to 100 psi. The permeation and separation is mainly controlled by diffusion instead of adsorption. CMS membrane experienced a decline in permeance, and an increase in selectivity over time under on-stream C3H6/C3H8 separation. This aging behavior is due to the reduction in effective pore size and porosity caused by oxygen chemisorption and physical aging of the membrane structure.
ContributorsMa, Xiaoli (Author) / Lin, Jerry (Thesis advisor) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2015
Description
Register file (RF) memory is important in low power system on chip (SOC) due to its
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.
inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic RFs. In this work, the various RFs designed for a microprocessor cache and register files are discussed. Comparison between static and dynamic RF power dissipation and timing characteristics is also presented. The relative timing and power advantages of the designs are shown to be dependent on the memory aspect ratio, i.e. array width and height.
ContributorsVashishtha, Vinay (Author) / Clark, Lawrence T. (Thesis advisor) / Seo, Jae-Sun (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Photocatalytic water splitting has been proposed as a promising way of generating carbon-neutral fuels from sunlight and water. In one approach, water decomposition is enabled by the use of functionalized nano-particulate photocatalyst composites. The atomic structures of the photocatalysts dictate their electronic and photonic structures, which are controlled by synthesis methods and may alter under reaction conditions. Characterizing these structures, especially the ones associated with photocatalysts’ surfaces, is essential because they determine the efficiencies of various reaction steps involved in photocatalytic water splitting. Due to its superior spatial resolution, (scanning) transmission electron microscopy (STEM/TEM), which includes various imaging and spectroscopic techniques, is a suitable tool for probing materials’ local atomic, electronic and optical structures. In this work, techniques specific for the study of photocatalysts are developed using model systems.
Nano-level structure-reactivity relationships as well as deactivation mechanisms of Ni core-NiO shell co-catalysts loaded on Ta2O5 particles are studied using an aberration-corrected TEM. It is revealed that nanometer changes in the shell thickness lead to significant changes in the H2 production. Also, deactivation of this system is found to be related to a photo-driven process resulting in the loss of the Ni core.
In addition, a special form of monochromated electron energy-loss spectroscopy (EELS), the so-called aloof beam EELS, is used to probe surface electronic states as well as light-particle interactions from model oxide nanoparticles. Surface states associated with hydrate species are analyzed using spectral simulations based on a dielectric theory and a density of states model. Geometry-induced optical-frequency resonant modes are excited using fast electrons in catalytically relevant oxides. Combing the spectral features detected in experiments with classical electrodynamics simulations, the underlying physics involved in this excitation process and the various influencing factors of the modes are investigated.
Finally, an in situ light illumination system is developed for an aberration-corrected environmental TEM to enable direct observation of atomic structural transformations of model photocatalysts while they are exposed to near reaction conditions.
Nano-level structure-reactivity relationships as well as deactivation mechanisms of Ni core-NiO shell co-catalysts loaded on Ta2O5 particles are studied using an aberration-corrected TEM. It is revealed that nanometer changes in the shell thickness lead to significant changes in the H2 production. Also, deactivation of this system is found to be related to a photo-driven process resulting in the loss of the Ni core.
In addition, a special form of monochromated electron energy-loss spectroscopy (EELS), the so-called aloof beam EELS, is used to probe surface electronic states as well as light-particle interactions from model oxide nanoparticles. Surface states associated with hydrate species are analyzed using spectral simulations based on a dielectric theory and a density of states model. Geometry-induced optical-frequency resonant modes are excited using fast electrons in catalytically relevant oxides. Combing the spectral features detected in experiments with classical electrodynamics simulations, the underlying physics involved in this excitation process and the various influencing factors of the modes are investigated.
Finally, an in situ light illumination system is developed for an aberration-corrected environmental TEM to enable direct observation of atomic structural transformations of model photocatalysts while they are exposed to near reaction conditions.
ContributorsLiu, Qianlang (Author) / Crozier, Peter A. (Thesis advisor) / Chan, Candace (Committee member) / Buttry, Daniel (Committee member) / Liu, Jingyue (Committee member) / Nemanich, Robert (Committee member) / Arizona State University (Publisher)
Created2018
Description
Static CMOS logic has remained the dominant design style of digital systems for
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.
ContributorsYang, Jinghua (Author) / Vrudhula, Sarma (Thesis advisor) / Barnaby, Hugh (Committee member) / Cao, Yu (Committee member) / Seo, Jae-Sun (Committee member) / Arizona State University (Publisher)
Created2018