ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 63
Description
Topological insulators with conducting surface states yet insulating bulk states have generated a lot of interest amongst the physics community due to their varied characteristics and possible applications. Doped topological insulators have presented newer physical states of matter where topological order co&ndashexists; with other physical properties (like magnetic order). The electronic states of these materials are very intriguing and pose problems and the possible solutions to understanding their unique behaviors. In this work, we use Electron Energy Loss Spectroscopy (EELS) – an analytical TEM tool to study both core&ndashlevel; and valence&ndashlevel; excitations in Bi2Se3 and Cu(doped)Bi2Se3 topological insulators. We use this technique to retrieve information on the valence, bonding nature, co-ordination and lattice site occupancy of the undoped and the doped systems. Using the reference materials Cu(I)Se and Cu(II)Se we try to compare and understand the nature of doping that copper assumes in the lattice. And lastly we utilize the state of the art monochromated Nion UltraSTEM 100 to study electronic/vibrational excitations at a record energy resolution from sub-nm regions in the sample.
ContributorsSubramanian, Ganesh (Author) / Spence, John (Thesis advisor) / Jiang, Nan (Committee member) / Chen, Tingyong (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2013
Description
Micro Electro Mechanical Systems (MEMS) is one of the fastest growing field in silicon industry. Low cost production is key for any company to improve their market share. MEMS testing is challenging since input to test a MEMS device require physical stimulus like acceleration, pressure etc. Also, MEMS device vary with process and requires calibration to make them reliable. This increases test cost and testing time. This challenge can be overcome by combining electrical stimulus based testing along with statistical analysis on MEMS response for electrical stimulus and also limited physical stimulus response data. This thesis proposes electrical stimulus based built in self test(BIST) which can be used to get MEMS data and later this data can be used for statistical analysis. A capacitive MEMS accelerometer is considered to test this BIST approach. This BIST circuit overhead is less and utilizes most of the standard readout circuit. This thesis discusses accelerometer response for electrical stimulus and BIST architecture. As a part of this BIST circuit, a second order sigma delta modulator has been designed. This modulator has a sampling frequency of 1MHz and bandwidth of 6KHz. SNDR of 60dB is achieved with 1Vpp differential input signal and 3.3V supply
ContributorsKundur, Vinay (Author) / Bakkaloglu, Bertan (Committee member) / Ozev, Sule (Committee member) / Kiaei, Sayfe (Committee member) / Arizona State University (Publisher)
Created2013
Description
Dealloying, the selective dissolution of an elemental component from an alloy, is an important corrosion mechanism and a technological significant means to fabricate nanoporous structures for a variety of applications. In noble metal alloys, dealloying proceeds above a composition dependent critical potential, and bi-continuous structure evolves "simultaneously" as a result of the interplay between percolation dissolution and surface diffusion. In contrast, dealloying in alloys that show considerable solid-state mass transport at ambient temperature is largely unexplored despite its relevance to nanoparticle catalysts and Li-ion anodes. In my dissertation, I discuss the behaviors of two alloy systems in order to elucidate the role of bulk lattice diffusion in dealloying. First, Mg-Cd alloys are chosen to show that when the dealloying is controlled by bulk diffusion, a new type of porosity - negative void dendrites will form, and the process mirrors electrodeposition. Then, Li-Sn alloys are studied with respect to the composition, particle size and dealloying rate effects on the morphology evolution. Under the right condition, dealloying of Li-Sn supported by percolation dissolution results in the same bi-continuous structure as nanoporous noble metals; whereas lattice diffusion through the otherwise "passivated" surface allows for dealloying with no porosity evolution. The interactions between bulk diffusion, surface diffusion and dissolution are revealed by chronopotentiometry and linear sweep voltammetry technics. The better understanding of dealloying from these experiments enables me to construct a brief review summarizing the electrochemistry and morphology aspects of dealloying as well as offering interpretations to new observations such as critical size effect and encased voids in nanoporous gold. At the end of the dissertation, I will describe a preliminary attempt to generalize the morphology evolution "rules of dealloying" to all solid-to-solid interfacial controlled phase transition process, demonstrating that bi-continuous morphologies can evolve regardless of the nature of parent phase.
ContributorsChen, Qing (Author) / Sieradzki, Karl (Thesis advisor) / Friesen, Cody (Committee member) / Buttry, Daniel (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2013
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
ContributorsSuh, Jounghyuk (Author) / Bakkaloglu, Bertan (Thesis advisor) / Cao, Yu (Committee member) / Ozev, Sule (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
Mobile platforms are becoming highly heterogeneous by combining a powerful multiprocessor system-on-chip (MpSoC) with numerous resources including display, memory, power management IC (PMIC), battery and wireless modems into a compact package. Furthermore, the MpSoC itself is a heterogeneous resource that integrates many processing elements such as CPU cores, GPU, video, image, and audio processors. As a result, optimization approaches targeting mobile computing needs to consider the platform at various levels of granularity.
Platform energy consumption and responsiveness are two major considerations for mobile systems since they determine the battery life and user satisfaction, respectively. In this work, the models for power consumption, response time, and energy consumption of heterogeneous mobile platforms are presented. Then, these models are used to optimize the energy consumption of baseline platforms under power, response time, and temperature constraints with and without introducing new resources. It is shown, the optimal design choices depend on dynamic power management algorithm, and adding new resources is more energy efficient than scaling existing resources alone. The framework is verified through actual experiments on Qualcomm Snapdragon 800 based tablet MDP/T. Furthermore, usage of the framework at both design and runtime optimization is also presented.
Platform energy consumption and responsiveness are two major considerations for mobile systems since they determine the battery life and user satisfaction, respectively. In this work, the models for power consumption, response time, and energy consumption of heterogeneous mobile platforms are presented. Then, these models are used to optimize the energy consumption of baseline platforms under power, response time, and temperature constraints with and without introducing new resources. It is shown, the optimal design choices depend on dynamic power management algorithm, and adding new resources is more energy efficient than scaling existing resources alone. The framework is verified through actual experiments on Qualcomm Snapdragon 800 based tablet MDP/T. Furthermore, usage of the framework at both design and runtime optimization is also presented.
ContributorsGupta, Ujjwala (Author) / Ogras, Umit Y. (Thesis advisor) / Ozev, Sule (Committee member) / Chakrabarti, Chaitali (Committee member) / Arizona State University (Publisher)
Created2014
Description
High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB.
The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS.
ContributorsJankunas, Benjamin (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2014
Description
Membrane-based gas separation is promising for efficient propylene/propane (C3H6/C3H8) separation with low energy consumption and minimum environment impact. Two microporous inorganic membrane candidates, MFI-type zeolite membrane and carbon molecular sieve membrane (CMS) have demonstrated excellent thermal and chemical stability. Application of these membranes into C3H6/C3H8 separation has not been well investigated. This dissertation presents fundamental studies on membrane synthesis, characterization and C3H6/C3H8 separation properties of MFI zeolite membrane and CMS membrane.
MFI zeolite membranes were synthesized on α-alumina supports by secondary growth method. Novel positron annihilation spectroscopy (PAS) techniques were used to non-destructively characterize the pore structure of these membranes. PAS reveals a bimodal pore structure consisting of intracrystalline zeolitic micropores of ~0.6 nm in diameter and irregular intercrystalline micropores of 1.4 to 1.8 nm in size for the membranes. The template-free synthesized membrane exhibited a high permeance but a low selectivity in C3H6/C3H8 mixture separation.
CMS membranes were synthesized by coating/pyrolysis method on mesoporous γ-alumina support. Such supports allow coating of thin, high-quality polymer films and subsequent CMS membranes with no infiltration into support pores. The CMS membranes show strong molecular sieving effect, offering a high C3H6/C3H8 mixture selectivity of ~30. Reduction in membrane thickness from 500 nm to 300 nm causes an increase in C3H8 permeance and He/N2 selectivity, but a decrease in the permeance of He, N2 and C3H6 and C3H6/C3H8 selectivity. This can be explained by the thickness dependent chain mobility of the polymer film resulting in final carbon membrane of reduced pore size with different effects on transport of gas of different sizes, including possible closure of C3H6-accessible micropores.
CMS membranes demonstrate excellent C3H6/C3H8 separation performance over a wide range of feed pressure, composition and operation temperature. No plasticization was observed at a feed pressure up to 100 psi. The permeation and separation is mainly controlled by diffusion instead of adsorption. CMS membrane experienced a decline in permeance, and an increase in selectivity over time under on-stream C3H6/C3H8 separation. This aging behavior is due to the reduction in effective pore size and porosity caused by oxygen chemisorption and physical aging of the membrane structure.
MFI zeolite membranes were synthesized on α-alumina supports by secondary growth method. Novel positron annihilation spectroscopy (PAS) techniques were used to non-destructively characterize the pore structure of these membranes. PAS reveals a bimodal pore structure consisting of intracrystalline zeolitic micropores of ~0.6 nm in diameter and irregular intercrystalline micropores of 1.4 to 1.8 nm in size for the membranes. The template-free synthesized membrane exhibited a high permeance but a low selectivity in C3H6/C3H8 mixture separation.
CMS membranes were synthesized by coating/pyrolysis method on mesoporous γ-alumina support. Such supports allow coating of thin, high-quality polymer films and subsequent CMS membranes with no infiltration into support pores. The CMS membranes show strong molecular sieving effect, offering a high C3H6/C3H8 mixture selectivity of ~30. Reduction in membrane thickness from 500 nm to 300 nm causes an increase in C3H8 permeance and He/N2 selectivity, but a decrease in the permeance of He, N2 and C3H6 and C3H6/C3H8 selectivity. This can be explained by the thickness dependent chain mobility of the polymer film resulting in final carbon membrane of reduced pore size with different effects on transport of gas of different sizes, including possible closure of C3H6-accessible micropores.
CMS membranes demonstrate excellent C3H6/C3H8 separation performance over a wide range of feed pressure, composition and operation temperature. No plasticization was observed at a feed pressure up to 100 psi. The permeation and separation is mainly controlled by diffusion instead of adsorption. CMS membrane experienced a decline in permeance, and an increase in selectivity over time under on-stream C3H6/C3H8 separation. This aging behavior is due to the reduction in effective pore size and porosity caused by oxygen chemisorption and physical aging of the membrane structure.
ContributorsMa, Xiaoli (Author) / Lin, Jerry (Thesis advisor) / Alford, Terry (Committee member) / Chan, Candace (Committee member) / Arizona State University (Publisher)
Created2015
Description
Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.
ContributorsLiu, Tao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Committee member) / Vermeire, Bert (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current Shunt Monitor (CSM) systems have various applications for precise current monitoring of those aforementioned applications. CSMs enable current measurement across an external sense resistor (RS) in series to current flow. Two different types of CSMs designed and characterized in this paper. First design used direct current reading method and the other design used indirect current reading method. Proposed CSM systems can sense power supply current ranging from 1mA to 200mA for the direct current reading topology and from 1mA to 500mA for the indirect current reading topology across a typical board Cu-trace resistance of 1 ohm with less than 10 µV input-referred offset, 0.3 µV/°C offset drift and 0.1% accuracy for both topologies. Proposed systems avoid using a costly zero-temperature coefficient (TC) sense resistor that is normally used in typical CSM systems. Instead, both of the designs used existing Cu-trace on the printed circuit board (PCB) in place of the costly resistor. The systems use chopper stabilization at the front-end amplifier signal path to suppress input-referred offset down to less than 10 µV. Switching current-mode (SI) FIR filtering technique is used at the instrumentation amplifier output to filter out the chopping ripple caused by input offset and flicker noise by averaging half of the phase 1 signal and the other half of the phase 2 signal. In addition, residual offset mainly caused by clock feed-through and charge injection of the chopper switches at the chopping frequency and its multiple frequencies notched out by the since response of the SI-FIR filter. A frequency domain Sigma Delta ADC which is used for the indirect current reading type design enables a digital interface to processor applications with minimally added circuitries to build a simple 1st order Sigma Delta ADC. The CSMs are fabricated on a 0.7µm CMOS process with 3 levels of metal, with maximum Vds tolerance of 8V and operates across a common mode range of 0 to 26V for the direct current reading type and of 0 to 30V for the indirect current reading type achieving less than 10nV/sqrtHz of flicker noise at 100 Hz for both approaches. By using a semi-digital SI-FIR filter, residual chopper offset is suppressed down to 0.5mVpp from a baseline of 8mVpp, which is equivalent to 25dB suppression.
ContributorsYeom, Hyunsoo (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Yu, Hongyu (Committee member) / Arizona State University (Publisher)
Created2011