ASU Electronic Theses and Dissertations
This collection includes most of the ASU Theses and Dissertations from 2011 to present. ASU Theses and Dissertations are available in downloadable PDF format; however, a small percentage of items are under embargo. Information about the dissertations/theses includes degree information, committee members, an abstract, supporting data or media.
In addition to the electronic theses found in the ASU Digital Repository, ASU Theses and Dissertations can be found in the ASU Library Catalog.
Dissertations and Theses granted by Arizona State University are archived and made available through a joint effort of the ASU Graduate College and the ASU Libraries. For more information or questions about this collection contact or visit the Digital Repository ETD Library Guide or contact the ASU Graduate College at gradformat@asu.edu.
Displaying 1 - 10 of 84
Description
This thesis addresses the issue of making an economic case for energy storage in power systems. Bulk energy storage has often been suggested for large scale electric power systems in order to levelize load; store energy when it is inexpensive and discharge energy when it is expensive; potentially defer transmission and generation expansion; and provide for generation reserve margins. As renewable energy resource penetration increases, the uncertainty and variability of wind and solar may be alleviated by bulk energy storage technologies. The quadratic programming function in MATLAB is used to simulate an economic dispatch that includes energy storage. A program is created that utilizes quadratic programming to analyze various cases using a 2010 summer peak load from the Arizona transmission system, part of the Western Electricity Coordinating Council (WECC). The MATLAB program is used first to test the Arizona test bed with a low level of energy storage to study how the storage power limit effects several optimization out-puts such as the system wide operating costs. Very high levels of energy storage are then added to see how high level energy storage affects peak shaving, load factor, and other system applications. Finally, various constraint relaxations are made to analyze why the applications tested eventually approach a constant value. This research illustrates the use of energy storage which helps minimize the system wide generator operating cost by "shaving" energy off of the peak demand.
ContributorsRuggiero, John (Author) / Heydt, Gerald T (Thesis advisor) / Datta, Rajib (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2013
Description
Underground cables have been widely used in big cities. This is because underground cables offer the benefits of reducing visual impact and the disturbance caused by bad weather (wind, ice, snow, and the lightning strikes). Additionally, when placing power lines underground, the maintenance costs can also be reduced as a result. The underground cable rating calculation is the most critical part of designing the cable construction and cable installation. In this thesis, three contributions regarding the cable ampacity study have been made. First, an analytical method for rating of underground cables has been presented. Second, this research also develops the steady state and transient ratings for Salt River Project (SRP) 69 kV underground system using the commercial software CYMCAP for several typical substations. Third, to find an alternative way to predict the cable ratings, three regression models have been built. The residual plot and mean square error for the three methods have been analyzed. The conclusion is dawn that the nonlinear regression model provides the sufficient accuracy of the cable rating prediction for SRP's typical installation.
ContributorsWang, Tong (Author) / Tylavsky, Daniel (Thesis advisor) / Karady, George G. (Committee member) / Holbert, Keith E. (Committee member) / Arizona State University (Publisher)
Created2013
Description
This thesis concerns the flashover issue of the substation insulators operating in a polluted environment. The outdoor insulation equipment used in the power delivery infrastructure encounter different types of pollutants due to varied environmental conditions. Various methods have been developed by manufacturers and researchers to mitigate the flashover problem. The application of Room Temperature Vulcanized (RTV) silicone rubber is one such favorable method as it can be applied over the already installed units. Field experience has already showed that the RTV silicone rubber coated insulators have a lower flashover probability than the uncoated insulators. The scope of this research is to quantify the improvement in the flashover performance. Artificial contamination tests were carried on station post insulators for assessing their performance. A factorial experiment design was used to model the flashover performance. The formulation included the severity of contamination and leakage distance of the insulator samples. Regression analysis was used to develop a mathematical model from the data obtained from the experiments. The main conclusion drawn from the study is that the RTV coated insulators withstood much higher levels of contamination even when the coating had lost its hydrophobicity. This improvement in flashover performance was found to be in the range of 20-40%. A much better flashover performance was observed when the coating recovered its hydrophobicity. It was also seen that the adhesion of coating was excellent even after many tests which involved substantial discharge activity.
ContributorsGholap, Vipul (Author) / Gorur, Ravi S (Thesis advisor) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2013
Description
Scaling of the classical planar MOSFET below 20 nm gate length is facing not only technological difficulties but also limitations imposed by short channel effects, gate and junction leakage current due to quantum tunneling, high body doping induced threshold voltage variation, and carrier mobility degradation. Non-classical multiple-gate structures such as double-gate (DG) FinFETs and surrounding gate field-effect-transistors (SGFETs) have good electrostatic integrity and are an alternative to planar MOSFETs for below 20 nm technology nodes. Circuit design with these devices need compact models for SPICE simulation. In this work physics based compact models for the common-gate symmetric DG-FinFET, independent-gate asymmetric DG-FinFET, and SGFET are developed. Despite the complex device structure and boundary conditions for the Poisson-Boltzmann equation, the core structure of the DG-FinFET and SGFET models, are maintained similar to the surface potential based compact models for planar MOSFETs such as SP and PSP. TCAD simulations show differences between the transient behavior and the capacitance-voltage characteristics of bulk and SOI FinFETs if the gate-voltage swing includes the accumulation region. This effect can be captured by a compact model of FinFETs only if it includes the contribution of both types of carriers in the Poisson-Boltzmann equation. An accurate implicit input voltage equation valid in all regions of operation is proposed for common-gate symmetric DG-FinFETs with intrinsic or lightly doped bodies. A closed-form algorithm is developed for solving the new input voltage equation including ambipolar effects. The algorithm is verified for both the surface potential and its derivatives and includes a previously published analytical approximation for surface potential as a special case when ambipolar effects can be neglected. The symmetric linearization method for common-gate symmetric DG-FinFETs is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFETs. The accuracy of the proposed technique is verified by comparison with exact results. An alternative and computationally efficient description of the boundary between the trigonometric and hyperbolic solutions of the Poisson-Boltzmann equation for the independent-gate asymmetric DG-FinFET is developed in terms of the Lambert W function. Efficient numerical algorithm is proposed for solving the input voltage equation. Analytical expressions for terminal charges of an independent-gate asymmetric DG-FinFET are derived. The new charge model is C-infinity continuous, valid for weak as well as for strong inversion condition of both the channels and does not involve the charge-sheet approximation. This is accomplished by developing the symmetric linearization method in a form that does not require identical boundary conditions at the two Si-SiO2 interfaces and allows for volume inversion in the DG-FinFET. Verification of the model is performed with both numerical computations and 2D TCAD simulations under a wide range of biasing conditions. The model is implemented in a standard circuit simulator through Verilog-A code. Simulation examples for both digital and analog circuits verify good model convergence and demonstrate the capabilities of new circuit topologies that can be implemented using independent-gate asymmetric DG-FinFETs.
ContributorsDessai, Gajanan (Author) / Gildenblat, Gennady (Committee member) / McAndrew, Colin (Committee member) / Cao, Yu (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2012
Description
Test cost has become a significant portion of device cost and a bottleneck in high volume manufacturing. Increasing integration density and shrinking feature sizes increased test time/cost and reduce observability. Test engineers have to put a tremendous effort in order to maintain test cost within an acceptable budget. Unfortunately, there is not a single straightforward solution to the problem. Products that are tested have several application domains and distinct customer profiles. Some products are required to operate for long periods of time while others are required to be low cost and optimized for low cost. Multitude of constraints and goals make it impossible to find a single solution that work for all cases. Hence, test development/optimization is typically design/circuit dependent and even process specific. Therefore, test optimization cannot be performed using a single test approach, but necessitates a diversity of approaches. This works aims at addressing test cost minimization and test quality improvement at various levels. In the first chapter of the work, we investigate pre-silicon strategies, such as design for test and pre-silicon statistical simulation optimization. In the second chapter, we investigate efficient post-silicon test strategies, such as adaptive test, adaptive multi-site test, outlier analysis, and process shift detection/tracking.
ContributorsYilmaz, Ender (Author) / Ozev, Sule (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Christen, Jennifer Blain (Committee member) / Arizona State University (Publisher)
Created2012
Description
Renewable portfolio standards prescribe for penetration of high amounts of re-newable energy sources (RES) that may change the structure of existing power systems. The load growth and changes in power flow caused by RES integration may result in re-quirements of new available transmission capabilities and upgrades of existing transmis-sion paths. Construction difficulties of new transmission lines can become a problem in certain locations. The increase of transmission line thermal ratings by reconductoring using High Temperature Low Sag (HTLS) conductors is a comparatively new technology introduced to transmission expansion. A special design permits HTLS conductors to operate at high temperatures (e.g., 200oC), thereby allowing passage of higher current. The higher temperature capability increases the steady state and emergency thermal ratings of the transmission line. The main disadvantage of HTLS technology is high cost. The high cost may place special emphasis on a thorough analysis of cost to benefit of HTLS technology im-plementation. Increased transmission losses in HTLS conductors due to higher current may be a disadvantage that can reduce the attractiveness of this method. Studies described in this thesis evaluate the expenditures for transmission line re-conductoring using HTLS and the consequent benefits obtained from the potential decrease in operating cost for thermally limited transmission systems. Studies performed consider the load growth and penetration of distributed renewable energy sources according to the renewable portfolio standards for power systems. An evaluation of payback period is suggested to assess the cost to benefit ratio of HTLS upgrades. The thesis also considers the probabilistic nature of transmission upgrades. The well-known Chebyshev inequality is discussed with an application to transmission up-grades. The Chebyshev inequality is proposed to calculate minimum payback period ob-tained from the upgrades of certain transmission lines. The cost to benefit evaluation of HTLS upgrades is performed using a 225 bus equivalent of the 2012 summer peak Arizona portion of the Western Electricity Coordi-nating Council (WECC).
ContributorsTokombayev, Askhat (Author) / Heydt, Gerald T. (Thesis advisor) / Sankar, Lalitha (Committee member) / Karady, George G. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates.
ContributorsYang, Chengen (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2014
Description
With increasing demand for System on Chip (SoC) and System in Package (SiP) design in computer and communication technologies, integrated inductor which is an essential passive component has been widely used in numerous integrated circuits (ICs) such as in voltage regulators and RF circuits. In this work, soft ferromagnetic core material, amorphous Co-Zr-Ta-B, was incorporated into on-chip and in-package inductors in order to scale down inductors and improve inductors performance in both inductance density and quality factor. With two layers of 500 nm Co-Zr-Ta-B films a 3.5X increase in inductance and a 3.9X increase in quality factor over inductors without magnetic films were measured at frequencies as high as 1 GHz. By laminating technology, up to 9.1X increase in inductance and more than 5X increase in quality factor (Q) were obtained from stripline inductors incorporated with 50 nm by 10 laminated films with a peak Q at 300 MHz. It was also demonstrated that this peak Q can be pushed towards high frequency as far as 1GHz by a combination of patterning magnetic films into fine bars and laminations. The role of magnetic vias in magnetic flux and eddy current control was investigated by both simulation and experiment using different patterning techniques and by altering the magnetic via width. Finger-shaped magnetic vias were designed and integrated into on-chip RF inductors improving the frequency of peak quality factor from 400 MHz to 800 MHz without sacrificing inductance enhancement. Eddy current and magnetic flux density in different areas of magnetic vias were analyzed by HFSS 3D EM simulation. With optimized magnetic vias, high frequency response of up to 2 GHz was achieved. Furthermore, the effect of applied magnetic field on on-chip inductors was investigated for high power applications. It was observed that as applied magnetic field along the hard axis (HA) increases, inductance maintains similar value initially at low fields, but decreases at larger fields until the magnetic films become saturated. The high frequency quality factor showed an opposite trend which is correlated to the reduction of ferromagnetic resonant absorption in the magnetic film. In addition, experiments showed that this field-dependent inductance change varied with different patterned magnetic film structures, including bars/slots and fingers structures. Magnetic properties of Co-Zr-Ta-B films on standard organic package substrates including ABF and polyimide were also characterized. Effects of substrate roughness and stress were analyzed and simulated which provide strategies for integrating Co-Zr-Ta-B into package inductors and improving inductors performance. Stripline and spiral inductors with Co-Zr-Ta-B films were fabricated on both ABF and polyimide substrates. Maximum 90% inductance increase in hundreds MHz frequency range were achieved in stripline inductors which are suitable for power delivery applications. Spiral inductors with Co-Zr-Ta-B films showed 18% inductance increase with quality factor of 4 at frequency up to 3 GHz.
ContributorsWu, Hao (Author) / Yu, Hongbin (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Cao, Yu (Committee member) / Chickamenahalli, Shamala (Committee member) / Arizona State University (Publisher)
Created2013
Description
The future grid will face challenges to meet an increased power demand by the consumers. Various solutions were studied to address this issue. One alternative to realize increased power flow in the grid is to use High Temperature Low Sag (HTLS) since it fulfills essential criteria of less sag and good material performance with temperature. HTLS conductors like Aluminum Conductor Composite Reinforced (ACCR) and Aluminum Conductor Carbon Composite (ACCC) are expected to face high operating temperatures of 150-200 degree Celsius in order to achieve the desired increased power flow. Therefore, it is imperative to characterize the material performance of these conductors with temperature. The work presented in this thesis addresses the characterization of carbon composite core based and metal matrix core based HTLS conductors. The thesis focuses on the study of variation of tensile strength of the carbon composite core with temperature and the level of temperature rise of the HTLS conductors due to fault currents cleared by backup protection. In this thesis, Dynamic Mechanical Analysis (DMA) was used to quantify the loss in storage modulus of carbon composite cores with temperature. It has been previously shown in literature that storage modulus is correlated to the tensile strength of the composite. Current temperature relationships of HTLS conductors were determined using the IEEE 738-2006 standard. Temperature rise of these conductors due to fault currents were also simulated. All simulations were performed using Microsoft Visual C++ suite. Tensile testing of metal matrix core was also performed. Results of DMA on carbon composite cores show that the storage modulus, hence tensile strength, decreases rapidly in the temperature range of intended use. DMA on composite cores subjected to heat treatment were conducted to investigate any changes in the variation of storage modulus curves. The experiments also indicates that carbon composites cores subjected to temperatures at or above 250 degree Celsius can cause permanent loss of mechanical properties including tensile strength. The fault current temperature analysis of carbon composite based conductors reveal that fault currents eventually cleared by backup protection in the event of primary protection failure can cause damage to fiber matrix interface.
ContributorsBanerjee, Koustubh (Author) / Gorur, Ravi (Committee member) / Karady, George G. (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2014
Description
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-Silicon bugs, minimizing design risk and cost. The unique features of the approach include 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; 3) compensation of AC performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45nm node that can map AMS modules across 22nm to 90nm technology nodes. A systematic emulation approach to map any analog transistor to 45nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for ID and less than 10% for Rout and Gm. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22nm and 90nm nodes with less than a 5% error. Several other 90nm and 22nm analog blocks are successfully emulated by the 45nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H). Further capabilities of PANDA are demonstrated by the first full-chip silicon of PANDA which is implemented on 65nm process This system consists of a 24×25 cell array, reconfigurable interconnect and configuration memory. The voltage and current reference circuits, op amps and a VCO with a phase interpolation circuit are emulated by PANDA.
ContributorsSuh, Jounghyuk (Author) / Bakkaloglu, Bertan (Thesis advisor) / Cao, Yu (Committee member) / Ozev, Sule (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2013