Barrett

Barrett, The Honors College at Arizona State University proudly showcases the work of undergraduate honors students by sharing this collection exclusively with the ASU community.

Barrett accepts high performing, academically engaged undergraduate students and works with them in collaboration with all of the other academic units at Arizona State University. All Barrett students complete a thesis or creative project which is an opportunity to explore an intellectual interest and produce an original piece of scholarly research. The thesis or creative project is supervised and defended in front of a faculty committee. Students are able to engage with professors who are nationally recognized in their fields and committed to working with honors students. Completing a Barrett thesis or creative project is an opportunity for undergraduate honors students to contribute to the ASU academic community in a meaningful way.

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RISC CPU Design

Description
This project's goal was to design a Central Processing Unit (CPU) incorporating a fairly large instruction set and a multistage pipeline design with the potential to be used in a multi-core system. The CPU was coded and synthesized with Verilog. This was accomplished by building on the CPU design from…

This project's goal was to design a Central Processing Unit (CPU) incorporating a fairly large instruction set and a multistage pipeline design with the potential to be used in a multi-core system. The CPU was coded and synthesized with Verilog. This was accomplished by building on the CPU design from fundamentals learned in CSE320 and increasing the instruction set to resemble a proper Reduced Instruction Set Computing (RISC) CPU system. A multistage pipeline was incorporated to the CPU to increase instruction throughput, or instructions per second. A major area of focus was on creating a multi-core design. The design used is master-slave in nature. The master core instructs the sub-cores where they should begin execution, the idea being that the operating system or kernel will be executing on the master core and the "user space" programs will be run on the sub-cores. The rationale behind this is that the system would specialize in running several small functions on all of its many supported cores. The system supports around 45 instructions, which include several types of jumps and branches (for changing the program counter based on conditions), arithmetic operations (addition, subtraction, or, and, etc.), and system calls (for controlling the core execution). The system has a very low Clocks per Instruction ratio (CPI), but to achieve this the second stage contains several modules and would most likely be a bottleneck for performance if implemented. The CPU is not perfect and contains a few errors and oversights, but the system as a whole functions as intended.
ContributorsKolden, Brian Andrew (Author) / Burger, Kevin (Thesis director) / Meuth, Ryan (Committee member) / Computer Science and Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-05