Barrett, The Honors College Thesis/Creative Project Collection
Barrett, The Honors College at Arizona State University proudly showcases the work of undergraduate honors students by sharing this collection exclusively with the ASU community.
Barrett accepts high performing, academically engaged undergraduate students and works with them in collaboration with all of the other academic units at Arizona State University. All Barrett students complete a thesis or creative project which is an opportunity to explore an intellectual interest and produce an original piece of scholarly research. The thesis or creative project is supervised and defended in front of a faculty committee. Students are able to engage with professors who are nationally recognized in their fields and committed to working with honors students. Completing a Barrett thesis or creative project is an opportunity for undergraduate honors students to contribute to the ASU academic community in a meaningful way.
This is a test plan document for Team Aegis' capstone project that has the goal of mitigating single event upsets in NAND flash memory caused by space radiation.
Radiation hardening of electronic devices is generally necessary when designing for the space environment. Non-volatile memory technologies are of particular concern when designing for the mitigation of radiation effects. Among other radiation effects, single-event upsets can create bit flips in non-volatile memories, leading to data corruption. In this paper, a Verilog implementation of a Reed-Solomon error-correcting code is considered for its ability to mitigate the effects of single-event upsets on non-volatile memories. This implementation is compared with the simpler procedure of using triple modular redundancy.
In collaboration with Moog Broad Reach and Arizona State University, a<br/>team of five undergraduate students designed a hardware design solution for<br/>protecting flash memory data in a spaced-based radioactive environment. Team<br/>Aegis have been working on the research, design, and implementation of a<br/>Verilog- and Python-based error correction code using a Reed-Solomon method<br/>to identify bit changes of error code. For an additional senior design project, a<br/>Python code was implemented that runs statistical analysis to identify whether<br/>the error correction code is more effective than a triple-redundancy check as well<br/>as determining if the presence of errors can be modeled by a regression model.