Barrett, The Honors College Thesis/Creative Project Collection
Barrett, The Honors College at Arizona State University proudly showcases the work of undergraduate honors students by sharing this collection exclusively with the ASU community.
Barrett accepts high performing, academically engaged undergraduate students and works with them in collaboration with all of the other academic units at Arizona State University. All Barrett students complete a thesis or creative project which is an opportunity to explore an intellectual interest and produce an original piece of scholarly research. The thesis or creative project is supervised and defended in front of a faculty committee. Students are able to engage with professors who are nationally recognized in their fields and committed to working with honors students. Completing a Barrett thesis or creative project is an opportunity for undergraduate honors students to contribute to the ASU academic community in a meaningful way.
Displaying 1 - 3 of 3
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- All Subjects: Memory
- Creators: Electrical Engineering Program
Description
Resistive Random Access Memory (RRAM) is an emerging type of non-volatile memory technology that seeks to replace FLASH memory. The RRAM crossbar array is advantageous in its relatively small cell area and faster read latency in comparison to NAND and NOR FLASH memory; however, the crossbar array faces design challenges of its own in sneak-path currents that prevent proper reading of memory stored in the RRAM cell. The Current Sensing Amplifier is one method of reading RRAM crossbar arrays. HSpice simulations are used to find the associated reading delays of the Current Sensing Amplifier with respect to various sizes of RRAM crossbar arrays, as well as the largest array size compatible for accurate reading. It is found that up to 1024x1024 arrays are achievable with a worst-case read delay of 815ps, and it is further likely 2048x2048 arrays are able to be read using the Current Sensing Amplifier. In comparing the Current Sensing Amplifier latency results with previously obtained latency results from the Voltage Sensing Amplifier, it is shown that the Voltage Sensing Amplifier reads arrays in sizes up to 256x256 faster while the Current Sensing Amplifier reads larger arrays faster.
ContributorsMoore, Jenna Barber (Author) / Yu, Shimeng (Thesis director) / Liu, Rui (Committee member) / Electrical Engineering Program (Contributor) / Barrett, The Honors College (Contributor)
Created2016-12
Description
This thesis outlines the hand-held memory characterization testing system that is to be created into a PCB (printed circuit board). The circuit is designed to apply voltages diagonally through a RRAM cell (32x32 memory array). The purpose of this sweep across the RRAM is to measure and calculate the high and low resistance state value over a specified amount of testing cycles. With each cell having a unique output of high and low resistance states a unique characterization of each RRAM cell is able to be developed. Once the memory is characterized, the specific RRAM cell that was tested is then able to be used in a varying amount of applications for different things based on its uniqueness. Due to an inability to procure a packaged RRAM cell, a Mock-RRAM was instead designed in order to emulate the same behavior found in a RRAM cell.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
ContributorsDobrin, Ryan Christopher (Co-author) / Halden, Matthew (Co-author) / Hall, Tanner (Co-author) / Barnaby, Hugh (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
Familiar Places: Ghosts of a Memory is a thesis exhibition, presented in Gallery 100 in Tempe, AZ, accompanied by a written investigation into the function of photography in the home and art. This project is a diaristic photographic record including images of myself, my family, my environment, and mementos or objects that embody family history. I am interested in what we hold onto to keep memories and create our "home". I moved frequently growing up so my sense of home became firmly grounded in family, tradition, and the things we kept close, making home a practiced space not a place. This thesis project explores how material culture, including photographs, is used in creating the space of the home. Questions regarding the nature of the photograph as a memory keeping device or memory trigger is investigated to understand their usefulness and accuracy to the memory. A deeper examination of the difference between an artist's photograph of family and home versus the family photograph is discussed and presented by utilizing installations in the exhibition. The photographs can be seen at www.gwendolynanne.com
ContributorsDavies, Gwendolyn Anne (Author) / Smith, Stephen Mark (Thesis director) / Danh, Binh (Committee member) / Loebenberg, Abby (Committee member) / School of Art (Contributor) / Barrett, The Honors College (Contributor)
Created2015-12