Matching Items (37)
Description
This dissertation addresses challenges pertaining to multi-junction (MJ) solar cells from material development to device design and characterization. Firstly, among the various methods to improve the energy conversion efficiency of MJ solar cells using, a novel approach proposed recently is to use II-VI (MgZnCd)(SeTe) and III-V (AlGaIn)(AsSb) semiconductors lattice-matched on GaSb or InAs substrates for current-matched subcells with minimal defect densities. CdSe/CdTe superlattices are proposed as a potential candidate for a subcell in the MJ solar cell designs using this material system, and therefore the material properties of the superlattices are studied. The high structural qualities of the superlattices are obtained from high resolution X-ray diffraction measurements and cross-sectional transmission electron microscopy images. The effective bandgap energies of the superlattices obtained from the photoluminescence (PL) measurements vary with the layer thicknesses, and are smaller than the bandgap energies of either the constituent material. Furthermore, The PL peak position measured at the steady state exhibits a blue shift that increases with the excess carrier concentration. These results confirm a strong type-II band edge alignment between CdSe and CdTe. The valence band offset between unstrained CdSe and CdTe is determined as 0.63 eV±0.06 eV by fitting the measured PL peak positions using the Kronig-Penney model. The blue shift in PL peak position is found to be primarily caused by the band bending effect based on self-consistent solutions of the Schrödinger and Poisson equations. Secondly, the design of the contact grid layout is studied to maximize the power output and energy conversion efficiency for concentrator solar cells. Because the conventional minimum power loss method used for the contact design is not accurate in determining the series resistance loss, a method of using a distributed series resistance model to maximize the power output is proposed for the contact design. It is found that the junction recombination loss in addition to the series resistance loss and shadowing loss can significantly affect the contact layout. The optimal finger spacing and maximum efficiency calculated by the two methods are close, and the differences are dependent on the series resistance and saturation currents of solar cells. Lastly, the accurate measurements of external quantum efficiency (EQE) are important for the design and development of MJ solar cells. However, the electrical and optical couplings between the subcells have caused EQE measurement artifacts. In order to interpret the measurement artifacts, DC and small signal models are built for the bias condition and the scan of chopped monochromatic light in the EQE measurements. Characterization methods are developed for the device parameters used in the models. The EQE measurement artifacts are found to be caused by the shunt and luminescence coupling effects, and can be minimized using proper voltage and light biases. Novel measurement methods using a pulse voltage bias or a pulse light bias are invented to eliminate the EQE measurement artifacts. These measurement methods are nondestructive and easy to implement. The pulse voltage bias or pulse light bias is superimposed on the conventional DC voltage and light biases, in order to control the operating points of the subcells and counterbalance the effects of shunt and luminescence coupling. The methods are demonstrated for the first time to effectively eliminate the measurement artifacts.
ContributorsLi, Jingjing (Author) / Zhang, Yong-Hang (Thesis advisor) / Tao, Meng (Committee member) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2012
Description
As the world energy demand increases, semiconductor devices with high energy conversion efficiency become more and more desirable. The energy conversion consists of two distinct processes, namely energy generation and usage. In this dissertation, novel multi-junction solar cells and light emitting diodes (LEDs) are proposed and studied for high energy conversion efficiency in both processes, respectively. The first half of this dissertation discusses the practically achievable energy conversion efficiency limit of solar cells. Since the demonstration of the Si solar cell in 1954, the performance of solar cells has been improved tremendously and recently reached 41.6% energy conversion efficiency. However, it seems rather challenging to further increase the solar cell efficiency. The state-of-the-art triple junction solar cells are analyzed to help understand the limiting factors. To address these issues, the monolithically integrated II-VI and III-V material system is proposed for solar cell applications. This material system covers the entire solar spectrum with a continuous selection of energy bandgaps and can be grown lattice matched on a GaSb substrate. Moreover, six four-junction solar cells are designed for AM0 and AM1.5D solar spectra based on this material system, and new design rules are proposed. The achievable conversion efficiencies for these designs are calculated using the commercial software package Silvaco with real material parameters. The second half of this dissertation studies the semiconductor luminescence refrigeration, which corresponds to over 100% energy usage efficiency. Although cooling has been realized in rare-earth doped glass by laser pumping, semiconductor based cooling is yet to be realized. In this work, a device structure that monolithically integrates a GaAs hemisphere with an InGaAs/GaAs quantum-well thin slab LED is proposed to realize cooling in semiconductor. The device electrical and optical performance is calculated. The proposed device then is fabricated using nine times photolithography and eight masks. The critical process steps, such as photoresist reflow and dry etch, are simulated to insure successful processing. Optical testing is done with the devices at various laser injection levels and the internal quantum efficiency, external quantum efficiency and extraction efficiency are measured.
ContributorsWu, Songnan (Author) / Zhang, Yong-Hang (Thesis advisor) / Menéndez, Jose (Committee member) / Ponce, Fernando (Committee member) / Belitsky, Andrei (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010
Description
To extend the lifetime of complementary metal-oxide-semiconductors (CMOS), emerging process techniques are being proposed to conquer the manufacturing difficulties. New structures and materials are proposed with superior electrical properties to traditional CMOS, such as strain technology and feedback field-effect transistor (FB-FET). To continue the design success and make an impact on leading products, advanced circuit design exploration must begin concurrently with early silicon development. Therefore, an accurate and scalable model is desired to correctly capture those effects and flexible to extend to alternative process choices. For example, strain technology has been successfully integrated into CMOS fabrication to improve transistor performance but the stress is non-uniformly distributed in the channel, leading to systematic performance variations. In this dissertation, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. On the other hand, semiconductor devices with self-feedback mechanisms are emerging as promising alternatives to CMOS. Fe-FET was proposed to improve the switching by integrating a ferroelectric material as gate insulator in a MOSFET structure. Under particular circumstances, ferroelectric capacitance is effectively negative, due to the negative slope of its polarization-electrical field curve. This property makes the ferroelectric layer a voltage amplifier to boost surface potential, achieving fast transition. A new threshold voltage model for Fe-FET is developed, and is further revealed that the impact of random dopant fluctuation (RDF) can be suppressed. Furthermore, through silicon via (TSV), a key technology that enables the 3D integration of chips, is studied. TSV structure is usually a cylindrical metal-oxide-semiconductors (MOS) capacitor. A piecewise capacitance model is proposed for 3D interconnect simulation. Due to the mismatch in coefficients of thermal expansion (CTE) among materials, thermal stress is observed in TSV process and impacts neighboring devices. The stress impact is investigated to support the interaction between silicon process and IC design at the early stage.
ContributorsWang, Chi-Chao (Author) / Cao, Yu (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Clark, Lawrence (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2011
Description
The object of this study is to investigate and improve the performance/stability of the flexible thin film transistors (TFTs) and to study the properties of metal oxide transparent conductive oxides for wide range of flexible electronic applications. Initially, a study has been done to improve the conductivity of ITO (indium tin oxide) films on PEN (polyethylene naphthalate) by inserting a thin layer of silver layer between two ITO layers. The multilayer with an optimum Ag mid-layer thickness, of 8 nm, exhibited excellent photopic average transmittance (~ 88 %), resistivity (~ 2.7 × 10-5 µ-cm.) and has the best Hackee figure of merit (41.0 × 10-3 Ω-1). The electrical conduction is dominated by two different scattering mechanisms depending on the thickness of the Ag mid-layer. Optical transmission is explained by scattering losses and absorption of light due to inter-band electronic transitions. A systematic study was carried out to improve the performance/stability of the TFTs on PEN. The performance and stability of a-Si:H and a-IZO (amorphous indium zinc oxide) TFTs were improved by performing a systematic low temperature (150 °C) anneals for extended times. For 96 hours annealed a-Si:H TFTs, the sub-threshold slope and off-current were reduced by a factor ~ 3 and by 2 orders of magnitude, respectively when compared to unannealed a-Si:H TFTs. For a-IZO TFTs, 48 hours of annealing is found to be the optimum time for the best performance and elevated temperature stability. These devices exhibit saturation mobility varying between 4.5-5.5 cm2/V-s, ION/IOFF ratio was 106 and a sub-threshold swing variation of 1-1.25 V/decade. An in-depth study on the mechanical and electromechanical stress response on the electrical properties of the a-IZO TFTs has also been investigated. Finally, the a-Si:H TFTs were exposed to gamma radiation to examine their radiation resistance. The interface trap density (Nit) values range from 5 to 6 × 1011 cm-2 for only electrical stress bias case. For "irradiation only" case, the Nit value increases from 5×1011 cm-2 to 2×1012 cm-2 after 3 hours of gamma radiation exposure, whereas it increases from 5×1011 cm-2 to 4×1012 cm-2 for "combined gamma and electrical stress".
ContributorsIndluru, Anil (Author) / Alford, Terry L. (Thesis advisor) / Schroder, Dieter (Committee member) / Krause, Stephen (Committee member) / Theodore, David (Committee member) / Arizona State University (Publisher)
Created2011
Description
Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250°C.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235°C.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
ContributorsSummers, Nicholas, M.S (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010
Description
As Energy needs grow and photovoltaics expand to meet humanity’s demand for electricity, waste modules will start building up. Tao et. al. propose a recycling process to recover all precious solar cell materials, a process estimated to generate a potential $15 billion in revenue by 2050. A key part of this process is metal recovery, and specifically, silver recovery. Silver recovery via electrowinning was studied using a hydrofluoric acid leachate/electrolyte. Bulk electrolysis trials were performed at varied voltages using a silver working electrode, silver pseudo-reference electrode and a graphite counter-electrode. The highest mass recovery achieved was 98.8% which occurred at 0.65 volts. Product purity was below 90% for all trials and coulombic efficiency never reached above 20%. The average energy consumption per gram of reduced silver was 2.16kWh/kg. Bulk electrolysis indicates that parasitic reactions are drawing power from the potentiostat and limiting the mass recovery of the system. In order to develop this process to the practical use stage, parasitic reactions must be eliminated, and product purity and power efficiency must improve. The system should be run in a vacuum environment and the reduction peaks in the cell should be characterized using cyclic voltammetry.
ContributorsTezak, Cooper R (Author) / Tao, Meng (Thesis director) / Phelan, Patrick (Committee member) / Chemical Engineering Program (Contributor) / School of International Letters and Cultures (Contributor) / Barrett, The Honors College (Contributor)
Created2020-12
Description
In Professor Meng Tao and Wen-His Huang's paper's [1,2] the recycling process to create a sustainable Photovoltaic (PV) industry is laid out. The process utilized to recycle the materials requires the use of three semi-problematic chemicals including: Sodium Hydroxide (NaOH), Nitric Acid (HNO3), and Hydrofluoric Acid (HF). By utilizing a combination of reverse osmosis filtration, pre-lime treatment, neutralization by combination, and mineral specific filtering the chemicals can either by recycled as Environmental Protection Agency (EPA) standardized waste water or profitable byproducts such as Sodium Nitrate (NaNO3). For the recycling of hydrofluoric acid, a combination of pre-lime coagulation, microfiltration and a spiral wound reverse osmosis (RO) system, less than 1mg/L in line with national standards for human consumption. The sodium hydroxide and nitric acid recycling process handles more contaminants that just the byproduct of the chemicals and manages this through a combination of multi-stage flash/vapor distillation along with a reverse osmosis filtration system. By utilizing both systems of recycling, a completely closed loop system for recycling silicon solar cells is laid out and creates a new standard for clean energy management.
ContributorsHaft, Brock Todd (Author) / Tao, Meng (Thesis director) / Augusto, Andre (Committee member) / Barrett, The Honors College (Contributor)
Created2016-12
Description
A general review of film growth with various mechanisms is given. Additives and their potential effects on film properties are also discussed. Experimental light-induced aluminum (Al) plating tool design is discussed. Light-induced electroplating of Al as the front electrode on the n-type emitter of silicon (Si) solar cells is proposed as a substitute for screen-printed Silver (Ag). The advantages and disadvantages of Al over copper (Cu) as a suitable Ag replacement are examined. Optimization of the power given to a green laser for silicon nitride (SiNx) anitreflection coating patterning is performed. Laser damage and contamination removal conditions on post-patterned cell surfaces are identified. Plating and post-annealing temperature effects on Al morphology and film resistivity are explored. Morphology and resistivity improvement of the Al film are also investigated through several plating additives. The lowest resistivity of 3.1 µΩ-cm is given by nicotinic acid. Laser induced damage to the cell emitter experimentally limits the contact resistivity between light-induced Al and Si to approximately 69 mΩ-cm2. Phosphorus pentachloride (PCl5) is introduced into the plating bath and improved the the contact resistivity between light induced Al and Si to a range of 0.1-1 mΩ-cm2. Secondary ion mass spectroscopy (SIMS) was performed on a film deposited with PCl5 and showed a phosphorus peak, indicating emitter phosphorus concentration may be the reason for the low contact resistivity between light-induced Al and Si. SEM also shows that PCl5 improves Al film density and plating throwing power. Post plating annealing performed at a temperature of 500°C allows Al to spike through the thin n-type emitter causing cell failure. Atmospheric moisture causes poor process reproducibility.
ContributorsRicci, Lewis (Author) / Tao, Meng (Thesis advisor) / Goryll, Michael (Committee member) / Kozicki, Michael (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2021
Description
This paper presents the electrolytic application of a load-matching PV system to produce green hydrogen. The system has proven its viability with purely resistive loads, and a static analysis has shown the performance potential of the system for electrolytic applications. This paper focuses on dynamic simulation of the load-matching PV system for green hydrogen production in SIMULINK. It is shown that an over 99% energy transfer efficiency from the PV array’s available energy to the electrolytic loads can be achieved under dynamic conditions for the system. The design parameters to optimize include the number of hydrogen cells per stack, the stack resistance, and the number of available stacks in the system. This system provides a simple but efficient approach for large-scale photovoltaic hydrogen production.
ContributorsPolo, Christian (Author) / Tao, Meng (Thesis director) / Parquette, William (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / Industrial, Systems & Operations Engineering Prgm (Contributor)
Created2022-05
Description
The silicon-based solar cell has been extensively deployed in photovoltaic industry and plays an important role in renewable energy industries. A more energy-efficient, environment-harmless and eco-friendly silicon production technique is required for price-competitive solar energy harvesting. Silicon electrorefining in molten salt is promising for the ultrapure solar-grade Si production. To avoid using highly corrosive fluoride salt, CaCl2-based salt is widely employed for silicon electroreduction. For Si electroreduction in CaCl2-based salt, CaO is usually added to enhance the solubility of SiO2. However, the existence of oxygen in molten salt could result in system corrosion, anode passivation and the co-deposition of secondary phases such as CaSiO3 and SiO2 at the cathode. This research focuses on the development of reusable oxygen-free CaCl2-based molten salt for solar-grade silicon electrorefining. A new multi-potential electropurification process has been proposed and proven to be more effective in impurities removal. The as-received salt and the salt after electrorefining have been electropurified. The inductively-coupled plasma mass spectrometry and cyclic voltammetry have been utilized to determine the impurities removal of electropurification. The salt after silicon electrorefining has been regenerated to its original purity level before by the multi-potential electropurification process, demonstrating the feasibility of a reusable salt by electropurification. In an oxygen-free CaCl2-based salt without silicon precursor, the silicon dissolved from the silicon anode can be successfully deposited at the cathode. The silicon anode has been operated for more than 50 hours without passivation in the oxygen-free system. Silicon ions start to be deposited after 0.17 g of silicon has been dissolved into the salt from the silicon anode. A 180 µm deposit with a silver-luster surface was obtained at the cathode. The main impurities in the silicon anode such as aluminum, iron and titanium were not found in the silicon deposits. No oxygen-containing secondary phases are detected in the silicon deposits. These results confirm the feasibility of silicon electrorefining in the oxygen-free CaCl2-based salt.
ContributorsTseng, Mao-Feng (Author) / Tao, Meng (Thesis advisor) / Kannan, Arunachala Mada (Committee member) / Mu, Linqin (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2023