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There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT The purpose of this study is to demonstrate that stable lipid bilayers can be set up on an array of silicon micropores and can be used as sites for self-inserting ion-channel proteins which can be studied independently of each other. In course of this study an acrylic based holder was designed and machined to ensure leak-free fluidic access to the silicon micropores and physical isolation of the individual array channels. To measure the ion-channel currents, we simulated, designed and manufactured low-noise transimpedance amplifiers and support circuits based on published patch clamp amplifier designs, using currently available surface-mount components. This was done in order to achieve a reduction in size and costs as well as isolation of individual channels without the need for multiplexing of the input. During the experiments performed, stable bilayers were formed across an array of four vertically mounted 30 µm silicon micropores and OmpF porins were added for self insertion in each of the bilayers. To further demonstrate the independence of these bilayer recording sites, the antibiotic Ampicillin (2.5 mM) was added to one of the fluidic wells. The ionic current in each of the wells was recorded simultaneously. Sub-conductance states of Ompf porin were observed in two of the measurement sites. In addition, the conductance steps in the site containing the antibiotic could be clearly seen to be larger compared to those of the unmodified site. This is due to the transient blocking of ion flow through the porin due to translocation of the antibiotic. Based on this demonstration, ion-channel array reconstitution is a potential method for efficient electrophysiological characterization of different types of ion-channels simultaneously as well as for studying membrane permeation processes.
ContributorsRamakrishnan, Shankar (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Blain Christen, Jennifer M (Committee member) / Arizona State University (Publisher)
Created2011
Description
In the last few years, significant advances in nanofabrication have allowed tailoring of structures and materials at a molecular level enabling nanofabrication with precise control of dimensions and organization at molecular length scales, a development leading to significant advances in nanoscale systems. Although, the direction of progress seems to follow the path of microelectronics, the fundamental physics in a nanoscale system changes more rapidly compared to microelectronics, as the size scale is decreased. The changes in length, area, and volume ratios due to reduction in size alter the relative influence of various physical effects determining the overall operation of a system in unexpected ways. One such category of nanofluidic structures demonstrating unique ionic and molecular transport characteristics are nanopores. Nanopores derive their unique transport characteristics from the electrostatic interaction of nanopore surface charge with aqueous ionic solutions. In this doctoral research cylindrical nanopores, in single and array configuration, were fabricated in silicon-on-insulator (SOI) using a combination of electron beam lithography (EBL) and reactive ion etching (RIE). The fabrication method presented is compatible with standard semiconductor foundries and allows fabrication of nanopores with desired geometries and precise dimensional control, providing near ideal and isolated physical modeling systems to study ion transport at the nanometer level. Ion transport through nanopores was characterized by measuring ionic conductances of arrays of nanopores of various diameters for a wide range of concentration of aqueous hydrochloric acid (HCl) ionic solutions. Measured ionic conductances demonstrated two distinct regimes based on surface charge interactions at low ionic concentrations and nanopore geometry at high ionic concentrations. Field effect modulation of ion transport through nanopore arrays, in a fashion similar to semiconductor transistors, was also studied. Using ionic conductance measurements, it was shown that the concentration of ions in the nanopore volume was significantly changed when a gate voltage on nanopore arrays was applied, hence controlling their transport. Based on the ion transport results, single nanopores were used to demonstrate their application as nanoscale particle counters by using polystyrene nanobeads, monodispersed in aqueous HCl solutions of different molarities. Effects of field effect modulation on particle transition events were also demonstrated.
ContributorsJoshi, Punarvasu (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Thesis advisor) / Spanias, Andreas (Committee member) / Saraniti, Marco (Committee member) / Arizona State University (Publisher)
Created2011
Description
Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250°C.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235°C.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
ContributorsSummers, Nicholas, M.S (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010
Description
Cubic boron nitride (c-BN), hexagonal boron nitride (h-BN), and semiconducting diamond all have physical properties that make them ideal materials for applications in high power and high frequency electronics, as well as radiation detectors. However, there is limited research on the unique properties and growth of c-BN or h-BN thin films. This dissertation addresses the deposition of c-BN via plasma enhanced chemical vapor deposition (PECVD) on boron doped diamond substrates. In-Situ X-ray photoelectron spectroscopy (XPS) is used to characterize the thickness and hexagonal to cubic ratio of boron nitride thin films. The effects of hydrogen concentration during the deposition of boron nitride are investigated. The boron nitride deposition rate is found to be dependent on the hydrogen gas flow. The sp2 to sp3 bonding is also found to be dependent on the hydrogen gas flow. Preferential growth of h-BN is observed when an excess of hydrogen is supplied to the reaction, while h-BN growth is suppressed when hydrogen flow is reduced to be the limiting reactant. Reduced hydrogen flow is also observed to promote preferential growth of c-BN.
The hydrogen limited reaction is used to deposit c-BN on single crystal (100) boron-doped diamond substrates. In-situ ultra-violet photoelectron spectroscopy (UPS) and XPS are used to deduce the valence band offset of the diamond/c-BN interface. A valence band offset of -0.3 eV is measured with the diamond VBM above the VBM of c-BN. This value is then discussed in context of previous experimental results and theoretical calculations.
Finally, UPS and XPS are used to characterize the surface states of phosphorus-doped diamond. Variations within the processing parameters for surface preparation and the effects on the electronic surface states are presented and discussed.
ContributorsBrown, Jesse (Author) / Nemanich, Robert J (Thesis advisor) / Alarcon, Ricardo (Committee member) / Lindsay, Stuart (Committee member) / Zaniewski, Anna (Committee member) / Arizona State University (Publisher)
Created2021
Description
The goal of this research work is to develop an understanding as well as modelling thermal effects in Si based nano-scale devices using a multiscale simulator tool. This tool has been developed within the research group at Arizona State University led by Professor Dr. Dragica Vasileska. Another research group, headed by Professor Dr. Thornton, also at Arizona State University, provided support with software tools, by not only laying out the physical experimental device, but also provided experimental data to verify the correctness and accuracy of the developed simulation tool. The tool consists of three separate but conjoined modules at different scales of representation. 1) A particle based, ensemble Monte Carlo (MC) simulation tool, which, in the long-time (electronic motion) limit, solves the Boltzmann transport equation (BTE) for electrons, coupled with an iterative solution to a two-dimensional (2D) Poisson’s equation, at the base device level. 2) Another device level thermal modeling tool which solves the energy balance equations accounting for carrier-phonon and phonon-phonon interactions and is integrated with the MC tool. 3) Lastly, a commercial technology computer aided design (TCAD) software, Silvaco is employed to incorporate the results from the above two tools to a circuit level, common-source dual-transistor circuit, where one of the devices acts a heater and the other as a sensor, to study the impacts of thermal heating. The results from this tool are fed back to the previous device level tools to iterate on, until a stable, unified electro-thermal equilibrium/result is obtained. This coupled electro-thermal approach was originally developed for an individual n-channel MOSFET (NMOS) device by Prof. Katerina Raleva and was extended to allow for multiple devices in tandem, thereby providing a platform for better and more accurate modeling of device behavior, analyzing circuit performance, and understanding thermal effects. Simulating this dual device circuit and analyzing the extracted voltage transfer and output characteristics verifies the efficacy of this methodology as the results obtained from this multi-scale, electro-thermal simulator tool, are found to be in good general agreement with the experimental data.
ContributorsQazi, Suleman Sami (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Thornton, Trevor J (Committee member) / Ferry, David K (Committee member) / Arizona State University (Publisher)
Created2021
Description
Diamond as a wide-bandgap (WBG) semiconductor material has distinct advantages for power electronics applications over Si and other WBG materials due to its high critical electric field (> 10 MV/cm), high electron and hole mobility (??=4500 cm2/V-s, ??=3800 cm2/V-s), high thermal conductivity (~22 W/cm-K) and large bandgap (5.47 eV). Owing to its remarkable properties, the application space of WBG materials has widened into areas requiring very high current, operating voltage and temperature. Remarkable progress has been made in demonstrating high breakdown voltage (>10 kV), ultra-high current density (> 100 kA/cm2) and ultra-high temperature (~1000oC) diamond devices, giving further evidence of diamond’s huge potential. However, despite the great success, fabricated diamond devices have not yet delivered diamond’s true potential. Some of the main reasons are high dopant activation energies, substantial bulk defect and trap densities, high contact resistance, and high leakage currents. A lack of complete understanding of the diamond specific device physics also impedes the progress in correct design approaches. The main three research focuses of this work are high power, high frequency and high temperature. Through the design, fabrication, testing, analysis and modeling of diamond p-i-n and Schottky diodes a milestone in diamond research is achieved and gain important theoretical understanding. In particular, a record highest current density in diamond diodes of ~116 kA/cm2 is demonstrated, RF characterization of diamond diodes is performed from 0.1 GHz to 25 GHz and diamond diodes are successfully tested in extreme environments of 500oC and ~93 bar of CO2 pressure. Theoretical models are constructed analytically and inii
Silvaco ATLAS including incomplete ionization and hopping mobility to explain space charge limited current phenomenon, effects of traps and Mott-Gurney dominated diode ???. A new interpretation of the Baliga figure of merit for WBG materials is also formulated and a new cubic relationship between ??? and breakdown voltage is established. Through Silvaco ATLAS modeling, predictions on the power limitation of diamond diodes in receiver-protector circuits is made and a range of self-heating effects is established. Poole-Frenkel emission and hopping conduction models are also utilized to analyze high temperature (500oC) leakage behavior of diamond diodes. Finally, diamond JFET simulations are performed and designs are proposed for high temperature – extreme environment applications.
ContributorsSurdi, Harshad (Author) / Goodnick, Stephen M (Thesis advisor) / Nemanich, Robert J (Committee member) / Thornton, Trevor J (Committee member) / Lyons, James R (Committee member) / Arizona State University (Publisher)
Created2022
Description
In this dissertation, atomic layer processing and surface characterization techniques were used to investigate surface conditions of wide band gap materials, gallium nitride (GaN) and gallium oxide (Ga2O3). These studies largely focused on mitigation and removal of defect formation induced by ions used in conventional plasma-based dry etching techniques. Band bending measured by x-ray photoelectron spectroscopy (XPS) was used to characterize charge compensation at the surface of GaN (0001) and determine densities of charged surface states produced by dry etching. Mitigation and removal of these dry-etch induced defects was investigated by varying inductively coupled plasma (ICP) etching conditions, performing thermal and plasma-based treatments, and development of a novel low-damage, self-limiting atomic layer etching (ALE) process to remove damaged material. Atomic layer deposition (ALD) and ALE techniques were developed for Ga2O3 using trimethylgallium (TMG). Ga2O3 was deposited by ALD on Si using TMG and O2 plasma with a growth rate of 1.0 ± 0.1 Å/cycle. Ga2O3 films were then etched using HF and TMG using a fully thermal ALE process with an etch rate of 0.9 ± Å/cycle. O2 plasma oxidation of GaN for surface conversion to Ga2O3 was investigated as a pathway for ALE of GaN using HF and TMG. This process was characterized using XPS, in situ multi-wavelength ellipsometry, and transmission electron microscopy. This study indicated that the etch rate was lower than anticipated, which was attributed to crystallinity of the converted surface oxide on GaN (0001).
ContributorsHatch, Kevin Andrew (Author) / Nemanich, Robert J (Thesis advisor) / Ponce, Fernando A (Committee member) / Smith, David J (Committee member) / Zhao, Yuji (Committee member) / Arizona State University (Publisher)
Created2021
Description
In this dissertation, the surface interactions of fluorine were studied during atomic layer deposition (ALD) and atomic layer etching (ALE) of wide band gap materials. To enable this research two high vacuum reactors were designed and constructed for thermal and plasma enhanced ALD and ALE, and they were equipped for in-situ process monitoring. Fluorine surface interactions were first studied in a comparison of thermal and plasma enhanced ALD (TALD and PEALD) of AlF3 thin films prepared using hydrogen fluoride (HF), trimethylaluminum (TMA), and H2-plasma. The ALD AlF3 films were compared ¬in-situ using ellipsometry and X-ray photoelectron spectroscopy (XPS). Ellipsometry showed a growth rate of 1.1 Å/ cycle and 0.7 Å/ cycle, at 100°C, for the TALD and PEALD AlF3 processes, respectively. XPS indicated the presence of Al-rich clusters within the PEALD film. The formation of the Al-rich clusters is thought to originate during the H2-plasma step of the PEALD process. The Al-rich clusters were not detected in the TALD AlF3 films. This study provided valuable insight on the role of fluorine in an ALD process.
Reactive ion etching is a common dry chemical etch process for fabricating GaN devices. However, the use of ions can induce various defects, which can degrade device performance. The development of low-damage post etch processes are essential for mitigating plasma induced damage. As such, two multistep ALE methods were implemented for GaN based on oxidation, fluorination, and ligand exchange. First, GaN surfaces were oxidized using either water vapor or O2-plasma exposures to produce a thin oxide layer. The oxide layer was addressed using alternating exposures of HF and TMG, which etch Ga2O3 films. Each ALE process was characterized using in-situ using ellipsometry and XPS and ex-situ transmission electron microscopy (TEM). XPS indicated F and O impurities remained on the etched surfaces. Ellipsometry and TEM showed a slight reduction in thickness. The very low ALE rate was interpreted as the inability of the Ga2O3 ALE process to fluorinate the ordered surface oxide on GaN (0001).
Overall, these results indicate HF is effective for the ALD of metal fluorides and the ALE of metal oxides.
ContributorsMessina, Daniel C (Author) / Nemanich, Robert J (Thesis advisor) / Goodnick, Stephen (Committee member) / Ponce, Fernando A (Committee member) / Smith, David (Committee member) / Arizona State University (Publisher)
Created2021
Description
Solid-state nanopore research, used in the field of biomolecule detection and separation, has developed rapidly during the last decade. An electric field generated from the nanopore membrane to the aperture surface by a bias voltage can be used to electrostatically control the transport of charges. This results in ionic current rectification that can be used for applications such as biomolecule filtration and DNA sequencing.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
ContributorsWang, Xiaofeng (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Christen, Jennifer M (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015