Matching Items (16)
Description
In this dissertation, the interface chemistry and electronic structure of plasma-enhanced atomic layer deposited (PEALD) dielectrics on GaN are investigated with x-ray and ultraviolet photoemission spectroscopy (XPS and UPS). Three interrelated issues are discussed in this study: (1) PEALD dielectric growth process optimization, (2) interface electronic structure of comparative PEALD dielectrics on GaN, and (3) interface electronic structure of PEALD dielectrics on Ga- and N-face GaN. The first study involved an in-depth case study of PEALD Al2O3 growth using dimethylaluminum isopropoxide, with a special focus on oxygen plasma effects. Saturated and self-limiting growth of Al2O3 films were obtained with an enhanced growth rate within the PEALD temperature window (25-220 ºC). The properties of Al2O3 deposited at various temperatures were characterized to better understand the relation between the growth parameters and film properties. In the second study, the interface electronic structures of PEALD dielectrics on Ga-face GaN films were measured. Five promising dielectrics (Al2O3, HfO2, SiO2, La2O3, and ZnO) with a range of band gap energies were chosen. Prior to dielectric growth, a combined wet chemical and in-situ H2/N2 plasma clean process was employed to remove the carbon contamination and prepare the surface for dielectric deposition. The surface band bending and band offsets were measured by XPS and UPS for dielectrics on GaN. The trends of the experimental band offsets on GaN were related to the dielectric band gap energies. In addition, the experimental band offsets were near the calculated values based on the charge neutrality level model. The third study focused on the effect of the polarization bound charge of the Ga- and N-face GaN on interface electronic structures. A surface pretreatment process consisting of a NH4OH wet chemical and an in-situ NH3 plasma treatment was applied to remove carbon contamination, retain monolayer oxygen coverage, and potentially passivate N-vacancy related defects. The surface band bending and polarization charge compensation of Ga- and N-face GaN were investigated. The surface band bending and band offsets were determined for Al2O3, HfO2, and SiO2 on Ga- and N-face GaN. Different dielectric thicknesses and post deposition processing were investigated to understand process related defect formation and/or reduction.
ContributorsYang, Jialing (Author) / Nemanich, Robert J (Thesis advisor) / Chen, Tingyong (Committee member) / Peng, Xihong (Committee member) / Ponce, Fernando (Committee member) / Smith, David (Committee member) / Arizona State University (Publisher)
Created2014
Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
In the last few years, significant advances in nanofabrication have allowed tailoring of structures and materials at a molecular level enabling nanofabrication with precise control of dimensions and organization at molecular length scales, a development leading to significant advances in nanoscale systems. Although, the direction of progress seems to follow the path of microelectronics, the fundamental physics in a nanoscale system changes more rapidly compared to microelectronics, as the size scale is decreased. The changes in length, area, and volume ratios due to reduction in size alter the relative influence of various physical effects determining the overall operation of a system in unexpected ways. One such category of nanofluidic structures demonstrating unique ionic and molecular transport characteristics are nanopores. Nanopores derive their unique transport characteristics from the electrostatic interaction of nanopore surface charge with aqueous ionic solutions. In this doctoral research cylindrical nanopores, in single and array configuration, were fabricated in silicon-on-insulator (SOI) using a combination of electron beam lithography (EBL) and reactive ion etching (RIE). The fabrication method presented is compatible with standard semiconductor foundries and allows fabrication of nanopores with desired geometries and precise dimensional control, providing near ideal and isolated physical modeling systems to study ion transport at the nanometer level. Ion transport through nanopores was characterized by measuring ionic conductances of arrays of nanopores of various diameters for a wide range of concentration of aqueous hydrochloric acid (HCl) ionic solutions. Measured ionic conductances demonstrated two distinct regimes based on surface charge interactions at low ionic concentrations and nanopore geometry at high ionic concentrations. Field effect modulation of ion transport through nanopore arrays, in a fashion similar to semiconductor transistors, was also studied. Using ionic conductance measurements, it was shown that the concentration of ions in the nanopore volume was significantly changed when a gate voltage on nanopore arrays was applied, hence controlling their transport. Based on the ion transport results, single nanopores were used to demonstrate their application as nanoscale particle counters by using polystyrene nanobeads, monodispersed in aqueous HCl solutions of different molarities. Effects of field effect modulation on particle transition events were also demonstrated.
ContributorsJoshi, Punarvasu (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Thesis advisor) / Spanias, Andreas (Committee member) / Saraniti, Marco (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT The purpose of this study is to demonstrate that stable lipid bilayers can be set up on an array of silicon micropores and can be used as sites for self-inserting ion-channel proteins which can be studied independently of each other. In course of this study an acrylic based holder was designed and machined to ensure leak-free fluidic access to the silicon micropores and physical isolation of the individual array channels. To measure the ion-channel currents, we simulated, designed and manufactured low-noise transimpedance amplifiers and support circuits based on published patch clamp amplifier designs, using currently available surface-mount components. This was done in order to achieve a reduction in size and costs as well as isolation of individual channels without the need for multiplexing of the input. During the experiments performed, stable bilayers were formed across an array of four vertically mounted 30 µm silicon micropores and OmpF porins were added for self insertion in each of the bilayers. To further demonstrate the independence of these bilayer recording sites, the antibiotic Ampicillin (2.5 mM) was added to one of the fluidic wells. The ionic current in each of the wells was recorded simultaneously. Sub-conductance states of Ompf porin were observed in two of the measurement sites. In addition, the conductance steps in the site containing the antibiotic could be clearly seen to be larger compared to those of the unmodified site. This is due to the transient blocking of ion flow through the porin due to translocation of the antibiotic. Based on this demonstration, ion-channel array reconstitution is a potential method for efficient electrophysiological characterization of different types of ion-channels simultaneously as well as for studying membrane permeation processes.
ContributorsRamakrishnan, Shankar (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Blain Christen, Jennifer M (Committee member) / Arizona State University (Publisher)
Created2011
Description
Solid-state nanopore research, used in the field of biomolecule detection and separation, has developed rapidly during the last decade. An electric field generated from the nanopore membrane to the aperture surface by a bias voltage can be used to electrostatically control the transport of charges. This results in ionic current rectification that can be used for applications such as biomolecule filtration and DNA sequencing.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
In this doctoral research, a voltage bias was applied on the device silicon layer of Silicon-on-Insulator (SOI) cylindrical single nanopore to analyze how the perpendicular gate electrical field affected the ionic current through the pore. The nanopore was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE) which are standard CMOS processes and can be integrated into any electronic circuit with massive production. The long cylindrical pore shape provides a larger surface area inside the aperture compared to other nanopores whose surface charge is of vital importance to ion transport.
Ionic transport through the nanopore was characterized by measuring the ionic conductance of the nanopore in aqueous hydrochloric acid and potassium chloride solutions under field effect modulation. The nanopores were separately coated with negatively charged thermal silicon oxide and positively charged aluminum oxide using Atomic Layer Deposition. Both layers worked as electrical insulation layers preventing leakage current once the substrate bias was applied. Different surface charges also provided different counterion-coion configurations. The transverse conductance of the nanopore at low electrolyte concentrations (<10-4 M) changed with voltage bias when the Debye length was comparable to the dimensions of the nanopore.
Ionic transport through nanopores coated with polyelectrolyte (PE) brushes were also investigated in ionic solutions with various pH values using Electrochemical Impedance spectroscopy (EIS). The pH sensitive poly[2–(dimethylamino) ethyl methacrylate] (PDMAEMA) PE brushes were integrated on the inner walls as well as the surface of the thermal oxidized SOI cylindrical nanopore using surface-initiated atom transfer radical polymerization (SI-ATRP). An equivalent circuit model was developed to extract conductive and resistive values of the nanopore in ionic solutions. The ionic conductance of PE coated nanopore was effectively rectified by varying the pH and gate bias.
ContributorsWang, Xiaofeng (Author) / Goryll, Michael (Thesis advisor) / Thornton, Trevor J (Committee member) / Christen, Jennifer M (Committee member) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2015
Description
Diamond and cubic boron nitride (c-BN) are ultra wide band gap semiconductors (Eg>3.4 eV) and share similar properties in various aspects, including being isoelectronic, a 1% lattice mismatch, large band gap, high thermal conductivity. Particularly, the negative electron affinity (NEA) of diamond and c-BN is an unusual property that has led to effects such as p-type surface conductivity, low temperature thermionic emission, and photon enhanced thermionic emission. In this dissertation, the interface chemistry and electronic structure of dielectrics on diamond and c-BN are investigated with X-ray and ultraviolet photoemission spectroscopy (XPS and UPS). The first study established that the surface conductive states could be established for thin Al2O3 on diamond using a post deposition H-plasma process. At each step of the atomic layer deposition (ALD) and plasma processing, the band alignment was characterized by in situ photoemission and related to interface charges. An interface layer between the diamond and dielectric layer was proposed to explain the surface conductivity. The second study further investigated the improvement of the hole mobility of surface conductive diamond. A thin layer of Al2O3 was employed as an interfacial layer between surface conductive hydrogen-terminated (H-terminated) diamond and MoO3 to increase the distance between the hole accumulation layer in diamond and negatively charged states in acceptor layer. With an interfacial layer, the ionic scattering, which was considered to limit the hole mobility, was reduced. By combining two oxides (Al2O3 and MoO3), the hole mobility and concentration were modulated by altering the thickness of the Al2O3 interfacial layer. The third study focused on the electronic structure of vanadium-oxide-terminated c-BN surfaces. The vanadium-oxide-termination was formed on c-BN by combining vanadium deposition using molecular beam deposition (MBD) and oxygen plasma treatment. After thermal annealing, a thermally stable NEA was achieved on c-BN. A model was proposed based on the deduced interface charge distribution to explain the establishment of an NEA.
ContributorsYang, Yu (Author) / Nemanich, Robert J (Thesis advisor) / McCartney, Martha (Committee member) / Ponce, Fernando (Committee member) / Qing, Quan (Committee member) / Arizona State University (Publisher)
Created2018
In-situ photoemission spectroscopy characterization of electronic states in semiconductor interfaces
Description
The electronic states of semiconductor interfaces have significant importance for semiconductor device performance, especially due to the continuing miniaturization of device technology.
The application of ultra high vacuum (UHV) enables the preparation and characterization of fresh and cleaned interfaces. In a UHV environment, photoemission spectroscopy (PES) provides a non-destructive method to measure the electronic band structure, which is a crucial component of interface properties.
In this dissertation, three semiconductor interfaces were studies to understand different effects on electronic states. The interfaces studied were freshly grown or pre-treated under UHV. Then in-situ PES measurements, including x-ray photoemission spectroscopy (XPS) and ultra-violet photoemission spectroscopy (UPS), were conducted to obtain electronic states information.
First, the CdTe/InSb (100) heterointerface was employed as a model interface for II-VI and III-V heterojunctions. It was suggested that an interface layer formed, which consisted of In-Te bonding. The non-octal bonding between In and Te atoms has donor-like behavior, which was proposed to result in an electron accumulation layer in InSb. A type-I heterointerface was observed. Second, Cu/ZnO interfaces were studied to understand the interface bonding and the role of polarization on ZnO interfaces. It was shown that on O-face ZnO (0001) and PEALD ZnO, copper contacts had ohmic behavior. However, on Zn-face ZnO (0001), a 0.3 eV Schottky barrier height was observed. The lower than expected barrier heights were attributed to oxygen vacancies introduced by Cu-O bonding during interface formation. In addition, it is suggested that the different barrier heights on two sides of ZnO (0001) are caused by the different behavior for the ZnO (0001) faces. Last, a pulse mode deposition method was applied for P-doped diamond growth on (100) diamond surfaces. Pretreatment effects were studied. It is suggested that an O/H plasma treatment or a short period of H-plasma and CH4/H2 plasma could yield a higher growth rate. PES measurements were conducted on H-terminated intrinsic diamond surface and P-doped/intrinsic diamond (100) interfaces. It was suggested that electronic states near the valence band maximum caused Fermi level pinning effects, independent of the diamond doping.
The application of ultra high vacuum (UHV) enables the preparation and characterization of fresh and cleaned interfaces. In a UHV environment, photoemission spectroscopy (PES) provides a non-destructive method to measure the electronic band structure, which is a crucial component of interface properties.
In this dissertation, three semiconductor interfaces were studies to understand different effects on electronic states. The interfaces studied were freshly grown or pre-treated under UHV. Then in-situ PES measurements, including x-ray photoemission spectroscopy (XPS) and ultra-violet photoemission spectroscopy (UPS), were conducted to obtain electronic states information.
First, the CdTe/InSb (100) heterointerface was employed as a model interface for II-VI and III-V heterojunctions. It was suggested that an interface layer formed, which consisted of In-Te bonding. The non-octal bonding between In and Te atoms has donor-like behavior, which was proposed to result in an electron accumulation layer in InSb. A type-I heterointerface was observed. Second, Cu/ZnO interfaces were studied to understand the interface bonding and the role of polarization on ZnO interfaces. It was shown that on O-face ZnO (0001) and PEALD ZnO, copper contacts had ohmic behavior. However, on Zn-face ZnO (0001), a 0.3 eV Schottky barrier height was observed. The lower than expected barrier heights were attributed to oxygen vacancies introduced by Cu-O bonding during interface formation. In addition, it is suggested that the different barrier heights on two sides of ZnO (0001) are caused by the different behavior for the ZnO (0001) faces. Last, a pulse mode deposition method was applied for P-doped diamond growth on (100) diamond surfaces. Pretreatment effects were studied. It is suggested that an O/H plasma treatment or a short period of H-plasma and CH4/H2 plasma could yield a higher growth rate. PES measurements were conducted on H-terminated intrinsic diamond surface and P-doped/intrinsic diamond (100) interfaces. It was suggested that electronic states near the valence band maximum caused Fermi level pinning effects, independent of the diamond doping.
ContributorsWang, Xingye (Author) / Nemanich, Robert J (Thesis advisor) / Chan, Candace (Committee member) / Ponce, Fernando (Committee member) / Holman, Zachary (Committee member) / Arizona State University (Publisher)
Created2018
Description
High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use.
In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.
In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.
ContributorsFang, Runchen (Author) / Barnaby, Hugh J (Thesis advisor) / Kozicki, Michael N (Thesis advisor) / Vasileska, Dragica (Committee member) / Thornton, Trevor J (Committee member) / Arizona State University (Publisher)
Created2018
Description
GaN and AlGaN have shown great potential in next-generation power and RF electronics. However, these devices are limited by reliability issues such as leakage current and current collapse that result from surface and interface states on GaN and AlGaN. This dissertation, therefore, examined these electronic states, focusing on the following two points:
First, the surface electronic state configuration was examined with regards to the polarization bound 1013 charges/cm2 that increases with aluminum content. This large bound charge requires compensation either externally by surface states or internally by the space charge regions as relates to band bending. In this work, band bending was measured after different surface treatments of GaN and AlGaN to determine the effects of specific surface states on the electronic state configuration. Results showed oxygen-terminated N-face GaN, Ga-face GaN, and Ga-face Al0.25Ga0.75N surface were characterized by similar band bending regardless of the polarization bound charge, suggesting a Fermi level pinning state ~0.4-0.8 eV below the conduction band minimum. On oxygen-free Ga-face GaN, Al0.15Ga0.85N, Al0.25Ga0.75N, and Al0.35Ga0.65N, band bending increased slightly with aluminum content and thus did not exhibit the same pinning behavior; however, there was still significant compensating charge on these surfaces (~1013 charges/cm2). This charge is likely related to nitrogen vacancies and/or gallium dangling bonds.
In addition, this wozrk investigated the interface electronic state configuration of dielectric/GaN and AlGaN interfaces with regards to deposition conditions and aluminum content. Specifically, oxygen plasma-enhanced atomic layer deposited (PEALD) was used to deposit SiO2. Growth temperature was shown to influence the film quality, where room temperature deposition produced the highest quality films in terms of electrical breakdown. In addition, the valence band offsets (VBOs) appeared to decrease with the deposition temperature, which likely related to an electric field across the Ga2O3 interfacial layer. VBOs were also determined with respect to aluminum content at the PEALD-SiO2/AlxGa1-xN interface, giving 3.0, 2.9, 2.9, and 2.8 eV for 0%, 15%, 25%, and 35% aluminum content, respectively—with corresponding conduction band offsets of 2.5, 2.2, 1.9, and 1.8 eV. This suggests the largest difference manifests in the conduction band, which is in agreement with the charge neutrality level model.
First, the surface electronic state configuration was examined with regards to the polarization bound 1013 charges/cm2 that increases with aluminum content. This large bound charge requires compensation either externally by surface states or internally by the space charge regions as relates to band bending. In this work, band bending was measured after different surface treatments of GaN and AlGaN to determine the effects of specific surface states on the electronic state configuration. Results showed oxygen-terminated N-face GaN, Ga-face GaN, and Ga-face Al0.25Ga0.75N surface were characterized by similar band bending regardless of the polarization bound charge, suggesting a Fermi level pinning state ~0.4-0.8 eV below the conduction band minimum. On oxygen-free Ga-face GaN, Al0.15Ga0.85N, Al0.25Ga0.75N, and Al0.35Ga0.65N, band bending increased slightly with aluminum content and thus did not exhibit the same pinning behavior; however, there was still significant compensating charge on these surfaces (~1013 charges/cm2). This charge is likely related to nitrogen vacancies and/or gallium dangling bonds.
In addition, this wozrk investigated the interface electronic state configuration of dielectric/GaN and AlGaN interfaces with regards to deposition conditions and aluminum content. Specifically, oxygen plasma-enhanced atomic layer deposited (PEALD) was used to deposit SiO2. Growth temperature was shown to influence the film quality, where room temperature deposition produced the highest quality films in terms of electrical breakdown. In addition, the valence band offsets (VBOs) appeared to decrease with the deposition temperature, which likely related to an electric field across the Ga2O3 interfacial layer. VBOs were also determined with respect to aluminum content at the PEALD-SiO2/AlxGa1-xN interface, giving 3.0, 2.9, 2.9, and 2.8 eV for 0%, 15%, 25%, and 35% aluminum content, respectively—with corresponding conduction band offsets of 2.5, 2.2, 1.9, and 1.8 eV. This suggests the largest difference manifests in the conduction band, which is in agreement with the charge neutrality level model.
ContributorsEller, Brianna (Author) / Nemanich, Robert J (Thesis advisor) / Chowdhury, Srabanti (Committee member) / McCartney, Martha (Committee member) / Ponce, Fernando (Committee member) / Smith, David (Committee member) / Arizona State University (Publisher)
Created2015
Description
Cubic boron nitride (c-BN) has potential for electronic applications as an electron emitter and serving as a base material for diodes, transistors, etc. However, there has been limited research on c-BN reported, and many of the electronic properties of c-BN and c-BN interfaces have yet to be reported. This dissertation focused on probing thin film c-BN deposited via plasma enhanced chemical vapor deposition (PECVD) with in situ photoelectron spectroscopy (PES). PES measurements were used to characterize the electronic properties of c-BN films and interfaces with vacuum and diamond. First, the interface between c-BN and vacuum were characterized with ultraviolet PES (UPS). UPS measurements indicated that as-deposited c-BN, H2 plasma treated c-BN, and annealed c-BN post H2 plasma treatment exhibited negative electron affinity surfaces. A dipole model suggested dipoles from H-terminated N surface sites were found to be responsible for the NEA surface. Then, Si was introduced into c-BN films to realize n-type doped c-BN. The valence structure and work function of c-BN:Si films were characterized with XPS and UPS measurements. Measurements were unable to confirm n-type character, and it is concluded that silicon nitride formation was the primary effect for the observations. Finally, XPS measurements were employed to measure the band offsets at the c-BN/diamond interface. Measurements indicated the valence band maximum (VBM) of c-BN was positioned ~0.8 eV above the VBM of diamond.
ContributorsShammas, Joseph (Author) / Nemanich, Robert J (Thesis advisor) / Ponce, Fernando (Committee member) / Chen, Tingyong (Committee member) / Chamberlin, Ralph (Committee member) / Arizona State University (Publisher)
Created2016