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Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
ContributorsHindman, Nathan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Microprocessors are the processing heart of any digital system and are central to all the technological advancements of the age including space exploration and monitoring. The demands of space exploration require a special class of microprocessors called radiation hardened microprocessors which are less susceptible to radiation present outside the earth's atmosphere, in other words their functioning is not disrupted even in presence of disruptive radiation. The presence of these particles forces the designers to come up with design techniques at circuit and chip levels to alleviate the errors which can be encountered in the functioning of microprocessors. Microprocessor evolution has been very rapid in terms of performance but the same cannot be said about its rad-hard counterpart. With the total data processing capability overall increasing rapidly, the clear lack of performance of the processors manifests as a bottleneck in any processing system. To design high performance rad-hard microprocessors designers have to overcome difficult design problems at various design stages i.e. Architecture, Synthesis, Floorplanning, Optimization, routing and analysis all the while maintaining circuit radiation hardness. The reference design `HERMES' is targeted at 90nm IBM G process and is expected to reach 500Mhz which is twice as fast any processor currently available. Chapter 1 talks about the mechanisms of radiation effects which cause upsets and degradation to the functioning of digital circuits. Chapter 2 gives a brief description of the components which are used in the design and are part of the consistent efforts at ASUVLSI lab culminating in this chip level implementation of the design. Chapter 3 explains the basic digital design ASIC flow and the changes made to it leading to a rad-hard specific ASIC flow used in implementing this chip. Chapter 4 talks about the triple mode redundant (TMR) specific flow which is used in the block implementation, delineating the challenges faced and the solutions proposed to make the flow work. Chapter 5 explains the challenges faced and solutions arrived at while using the top-level flow described in chapter 3. Chapter 6 puts together the results and analyzes the design in terms of basic integrated circuit design constraints.
ContributorsRamamurthy, Chandarasekaran (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh J (Committee member) / Mayhew, David (Committee member) / Arizona State University (Publisher)
Created2013
Description
Thin film transistors (TFTs) are being used in a wide variety of applications such as image sensors, radiation detectors, as well as for use in liquid crystal displays. However, there is a conspicuous absence of interface electronics for bridging the gap between the flexible sensors and digitized displays. Hence is the need to build the same. In this thesis, the feasibility of building mixed analog circuits in TFTs are explored and demonstrated. A flexible CMOS op-amp is demonstrated using a-Si:H and pentacene TFTs. The achieved performance is ¡Ö 50 dB of DC open loop gain with unity gain frequency (UGF) of 7 kHz. The op-amp is built on the popular 2 stage topology with the 2nd stage being cascoded to provide sufficient gain. A novel biasing circuit was successfully developed modifying the gm biasing circuit to retard the performance degradation as the TFTs aged. A switched capacitor 7 bit DAC was developed in only nMOS topology using a-Si:H TFTs, based on charge sharing concept. The DAC achieved a maximum differential non-linearity (DNL) of 0.6 least significant bit (LSB), while the maximum integral non-linearity (INL) was 1 LSB. TFTs were used as switches in this architecture; as a result the performance was quite unchanged even as the TFTs degraded. A 5 bit fully flash ADC was also designed using all nMOS a-Si:H TFTs. Gray coding was implemented at the output to avoid errors due to comparator meta-stability. Finally a 5 bit current steering DAC was also built using all nMOS a-Si:H TFTs. However, due to process variation, the DNL was increased to 1.2 while the INL was about 1.8 LSB. Measurements were made on the external stress effects on zinc indium oxide (ZIO) TFTs. Electrically induced stresses were studied applying DC bias on the gate and drain. These stresses shifted the device characteristics like threshold voltage and mobility. The TFTs were then mechanically stressed by stretching them across cylindrical structures of various radii. Both the subthreshold swing and mobility underwent significant changes when the stress was tensile while the change was minor under compressive stress, applied parallel to channel length.
ContributorsDey, Aritra (Author) / Allee, David R. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Garrity, Douglas A (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence T (Committee member) / Arizona State University (Publisher)
Created2011
Description
The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
ContributorsMaurya, Satendra Kumar (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Vrudhula, Sarma (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Circuits on smaller technology nodes become more vulnerable to radiation-induced upset. Since this is a major problem for electronic circuits used in space applications, designers have a variety of solutions in hand. Radiation hardening by design (RHBD) is an approach, where electronic components are designed to work properly in certain radiation environments without the use of special fabrication processes. This work focuses on the cache design for a high performance microprocessor. The design tries to mitigate radiation effects like SEE, on a commercial foundry 45 nm SOI process. The design has been ported from a previously done cache design at the 90 nm process node. The cache design is a 16 KB, 4 way set associative, write-through design that uses a no-write allocate policy. The cache has been tested to write and read at above 2 GHz at VDD = 0.9 V. Interleaved layout, parity protection, dual redundancy, and checking circuits are used in the design to achieve radiation hardness. High speed is accomplished through the use of dynamic circuits and short wiring routes wherever possible. Gated clocks and optimized wire connections are used to reduce power. Structured methodology is used to build up the entire cache.
ContributorsXavier, Jerin (Author) / Clark, Lawrence T (Thesis advisor) / Cao, Yu (Committee member) / Allee, David R. (Committee member) / Arizona State University (Publisher)
Created2012
Description
Clock generation and distribution are essential to CMOS microchips, providing synchronization to external devices and between internal sequential logic. Clocks in microprocessors are highly vulnerable to single event effects and designing reliable energy efficient clock networks for mission critical applications is a major challenge. This dissertation studies the basics of radiation hardening, essentials of clock design and impact of particle strikes on clocks in detail and presents design techniques for hardening complete clock systems in digital ICs.
Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse clocked latches and physical design methodologies for using TMR master-slave flip-flops in application specific ICs (ASICs) are proposed. A novel temporal pulse clocked latch design for low power radiation hardened applications is also proposed. Techniques for designing custom RHBD clock distribution networks (clock spines) and ASIC clock trees for a radiation hardened microprocessor using standard CAD tools are presented. A framework for analyzing the vulnerabilities of clock trees in general, and study the parameters that contribute the most to the tree’s failure, including impact on controlled latches is provided. This is then used to design an integrated temporally redundant clock tree and pulse clocked flip-flop based clocking scheme that is robust to single event transients (SETs) and single event upsets (SEUs). Subsequently, designing robust clock delay lines for use in double data rate (DDRx) memory applications is studied in detail. Several modules of the proposed radiation hardened all-digital delay locked loop are designed and studied. Many of the circuits proposed in this entire body of work have been implemented and tested on a standard low-power 90-nm process.
Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse clocked latches and physical design methodologies for using TMR master-slave flip-flops in application specific ICs (ASICs) are proposed. A novel temporal pulse clocked latch design for low power radiation hardened applications is also proposed. Techniques for designing custom RHBD clock distribution networks (clock spines) and ASIC clock trees for a radiation hardened microprocessor using standard CAD tools are presented. A framework for analyzing the vulnerabilities of clock trees in general, and study the parameters that contribute the most to the tree’s failure, including impact on controlled latches is provided. This is then used to design an integrated temporally redundant clock tree and pulse clocked flip-flop based clocking scheme that is robust to single event transients (SETs) and single event upsets (SEUs). Subsequently, designing robust clock delay lines for use in double data rate (DDRx) memory applications is studied in detail. Several modules of the proposed radiation hardened all-digital delay locked loop are designed and studied. Many of the circuits proposed in this entire body of work have been implemented and tested on a standard low-power 90-nm process.
ContributorsChellappa, Srivatsan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
The inherent risk in testing drugs has been hotly debated since the government first started regulating the drug industry in the early 1900s. Who can assume the risks associated with trying new pharmaceuticals is unclear when looked at through society's lens. In the mid twentieth century, the US Food and Drug Administration (FDA) published several guidance documents encouraging researchers to exclude women from early clinical drug research. The motivation to publish those documents and the subsequent guidance documents in which the FDA and other regulatory offices established their standpoints on women in drug research may have been connected to current events at the time. The problem of whether women should be involved in drug research is a question of who can assume risk and who is responsible for disseminating what specific kinds of information. The problem tends to be framed as one that juxtaposes the health of women and fetuses and sets their health as in opposition. That opposition, coupled with the inherent uncertainty in testing drugs, provides for a complex set of issues surrounding consent and access to information.
ContributorsMeek, Caroline Jane (Author) / Maienschein, Jane (Thesis director) / Brian, Jennifer (Committee member) / School of Life Sciences (Contributor) / Sanford School of Social and Family Dynamics (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
Social-emotional learning (SEL) methods are beginning to receive global attention in primary school education, yet the dominant emphasis on implementing these curricula is in high-income, urbanized areas. Consequently, the unique features of developing and integrating such methods in middle- or low-income rural areas are unclear. Past studies suggest that students exposed to SEL programs show an increase in academic performance, improved ability to cope with stress, and better attitudes about themselves, others, and school, but these curricula are designed with an urban focus. The purpose of this study was to conduct a needs-based analysis to investigate components specific to a SEL curriculum contextualized to rural primary schools. A promising organization committed to rural educational development is Barefoot College, located in Tilonia, Rajasthan, India. In partnership with Barefoot, we designed an ethnographic study to identify and describe what teachers and school leaders consider the highest needs related to their students' social and emotional education. To do so, we interviewed 14 teachers and school leaders individually or in a focus group to explore their present understanding of “social-emotional learning” and the perception of their students’ social and emotional intelligence. Analysis of this data uncovered common themes among classroom behaviors and prevalent opportunities to address social and emotional well-being among students. These themes translated into the three overarching topics and eight sub-topics explored throughout the curriculum, and these opportunities guided the creation of the 21 modules within it. Through a design-based research methodology, we developed a 40-hour curriculum by implementing its various modules within seven Barefoot classrooms alongside continuous reiteration based on teacher feedback and participant observation. Through this process, we found that student engagement increased during contextualized SEL lessons as opposed to traditional methods. In addition, we found that teachers and students preferred and performed better with an activities-based approach. These findings suggest that rural educators must employ particular teaching strategies when addressing SEL, including localized content and an experiential-learning approach. Teachers reported that as their approach to SEL shifted, they began to unlock the potential to build self-aware, globally-minded students. This study concludes that social and emotional education cannot be treated in a generalized manner, as curriculum development is central to the teaching-learning process.
ContributorsBucker, Delaney Sue (Author) / Carrese, Susan (Thesis director) / Barab, Sasha (Committee member) / School of Life Sciences (Contributor, Contributor) / School of Civic & Economic Thought and Leadership (Contributor) / School of International Letters and Cultures (Contributor) / Barrett, The Honors College (Contributor)
Created2020-05
Description
As of 2019, 30 US states have adopted abortion-specific informed consent laws that require state health departments to develop and disseminate written informational materials to patients seeking an abortion. Abortion is the only medical procedure for which states dictate the content of informed consent counseling. State abortion counseling materials have been criticized for containing inaccurate and misleading information, but overall, informed consent laws for abortion do not often receive national attention. The objective of this project was to determine the importance of informed consent laws to achieving the larger goal of dismantling the right to abortion. I found that informed consent counseling materials in most states contain a full timeline of fetal development, along with information about the risks of abortion, the risks of childbirth, and alternatives to abortion. In addition, informed consent laws for abortion are based on model legislation called the “Women’s Right to Know Act” developed by Americans United for Life (AUL). AUL calls itself the legal architect of the pro-life movement and works to pass laws at the state level that incrementally restrict abortion access so that it gradually becomes more difficult to exercise the right to abortion established by Roe v. Wade. The “Women’s Right to Know Act” is part of a larger package of model legislation called the “Women’s Protection Project,” a cluster of laws that place restrictions on abortion providers, purportedly to protect women, but actually to decrease abortion access. “Women’s Right to Know” counseling laws do not directly deny access to abortion, but they do reinforce key ideas important to the anti-abortion movement, like the concept of fetal personhood, distrust in medical professionals, the belief that pregnant people cannot be fully autonomous individuals, and the belief that abortion is not an ordinary medical procedure and requires special government oversight. “Women’s Right to Know” laws use the language of informed consent and the purported goal of protecting women to legitimize those ideas, and in doing so, they significantly undermine the right to abortion. The threat to abortion rights posed by laws like the “Women’s Right to Know” laws indicates the need to reevaluate and strengthen our ethical defense of the right to abortion.
ContributorsVenkatraman, Richa (Author) / Maienschein, Jane (Thesis director) / Brian, Jennifer (Thesis director) / Abboud, Carolina (Committee member) / Historical, Philosophical & Religious Studies (Contributor) / School of Life Sciences (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2020-05
Description
Turbidity is a known problem for UV water treatment systems as suspended particles can shield contaminants from the UV radiation. UV systems that utilize a reflective radiation chamber may be able to decrease the impact of turbidity on the efficacy of the system. The purpose of this study was to determine how kaolin clay and gram flour turbidity affects inactivation of Escherichia coli (E. coli) when using a UV system with a reflective chamber. Both sources of turbidity were shown to reduce the inactivation of E. coli with increasing concentrations. Overall, it was shown that increasing kaolin clay turbidity had a consistent effect on reducing UV inactivation across UV doses. Log inactivation was reduced by 1.48 log for the low UV dose and it was reduced by at least 1.31 log for the low UV dose. Gram flour had a similar effect to the clay at the lower UV dose, reducing log inactivation by 1.58 log. At the high UV dose, there was no change in UV inactivation with an increase in turbidity. In conclusion, turbidity has a significant impact on the efficacy of UV disinfection. Therefore, removing turbidity from water is an essential process to enhance UV efficiency for the disinfection of microbial pathogens.
ContributorsMalladi, Rohith (Author) / Abbaszadegan, Morteza (Thesis director) / Alum, Absar (Committee member) / Fox, Peter (Committee member) / School of Human Evolution & Social Change (Contributor) / School of Life Sciences (Contributor) / Barrett, The Honors College (Contributor)
Created2020-05