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Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
ContributorsHindman, Nathan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Microprocessors are the processing heart of any digital system and are central to all the technological advancements of the age including space exploration and monitoring. The demands of space exploration require a special class of microprocessors called radiation hardened microprocessors which are less susceptible to radiation present outside the earth's atmosphere, in other words their functioning is not disrupted even in presence of disruptive radiation. The presence of these particles forces the designers to come up with design techniques at circuit and chip levels to alleviate the errors which can be encountered in the functioning of microprocessors. Microprocessor evolution has been very rapid in terms of performance but the same cannot be said about its rad-hard counterpart. With the total data processing capability overall increasing rapidly, the clear lack of performance of the processors manifests as a bottleneck in any processing system. To design high performance rad-hard microprocessors designers have to overcome difficult design problems at various design stages i.e. Architecture, Synthesis, Floorplanning, Optimization, routing and analysis all the while maintaining circuit radiation hardness. The reference design `HERMES' is targeted at 90nm IBM G process and is expected to reach 500Mhz which is twice as fast any processor currently available. Chapter 1 talks about the mechanisms of radiation effects which cause upsets and degradation to the functioning of digital circuits. Chapter 2 gives a brief description of the components which are used in the design and are part of the consistent efforts at ASUVLSI lab culminating in this chip level implementation of the design. Chapter 3 explains the basic digital design ASIC flow and the changes made to it leading to a rad-hard specific ASIC flow used in implementing this chip. Chapter 4 talks about the triple mode redundant (TMR) specific flow which is used in the block implementation, delineating the challenges faced and the solutions proposed to make the flow work. Chapter 5 explains the challenges faced and solutions arrived at while using the top-level flow described in chapter 3. Chapter 6 puts together the results and analyzes the design in terms of basic integrated circuit design constraints.
ContributorsRamamurthy, Chandarasekaran (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Barnaby, Hugh J (Committee member) / Mayhew, David (Committee member) / Arizona State University (Publisher)
Created2013
Description
Thin film transistors (TFTs) are being used in a wide variety of applications such as image sensors, radiation detectors, as well as for use in liquid crystal displays. However, there is a conspicuous absence of interface electronics for bridging the gap between the flexible sensors and digitized displays. Hence is the need to build the same. In this thesis, the feasibility of building mixed analog circuits in TFTs are explored and demonstrated. A flexible CMOS op-amp is demonstrated using a-Si:H and pentacene TFTs. The achieved performance is ¡Ö 50 dB of DC open loop gain with unity gain frequency (UGF) of 7 kHz. The op-amp is built on the popular 2 stage topology with the 2nd stage being cascoded to provide sufficient gain. A novel biasing circuit was successfully developed modifying the gm biasing circuit to retard the performance degradation as the TFTs aged. A switched capacitor 7 bit DAC was developed in only nMOS topology using a-Si:H TFTs, based on charge sharing concept. The DAC achieved a maximum differential non-linearity (DNL) of 0.6 least significant bit (LSB), while the maximum integral non-linearity (INL) was 1 LSB. TFTs were used as switches in this architecture; as a result the performance was quite unchanged even as the TFTs degraded. A 5 bit fully flash ADC was also designed using all nMOS a-Si:H TFTs. Gray coding was implemented at the output to avoid errors due to comparator meta-stability. Finally a 5 bit current steering DAC was also built using all nMOS a-Si:H TFTs. However, due to process variation, the DNL was increased to 1.2 while the INL was about 1.8 LSB. Measurements were made on the external stress effects on zinc indium oxide (ZIO) TFTs. Electrically induced stresses were studied applying DC bias on the gate and drain. These stresses shifted the device characteristics like threshold voltage and mobility. The TFTs were then mechanically stressed by stretching them across cylindrical structures of various radii. Both the subthreshold swing and mobility underwent significant changes when the stress was tensile while the change was minor under compressive stress, applied parallel to channel length.
ContributorsDey, Aritra (Author) / Allee, David R. (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Garrity, Douglas A (Committee member) / Song, Hongjiang (Committee member) / Clark, Lawrence T (Committee member) / Arizona State University (Publisher)
Created2011
Description
The geometric growth in the integrated circuit technology due to transistor scaling also with system-on-chip design strategy, the complexity of the integrated circuit has increased manifold. Short time to market with high reliability and performance is one of the most competitive challenges. Both custom and ASIC design methodologies have evolved over the time to cope with this but the high manual labor in custom and statistic design in ASIC are still causes of concern. This work proposes a new circuit design strategy that focuses mostly on arrayed structures like TLB, RF, Cache, IPCAM etc. that reduces the manual effort to a great extent and also makes the design regular, repetitive still achieving high performance. The method proposes making the complete design custom schematic but using the standard cells. This requires adding some custom cells to the already exhaustive library to optimize the design for performance. Once schematic is finalized, the designer places these standard cells in a spreadsheet, placing closely the cells in the critical paths. A Perl script then generates Cadence Encounter compatible placement file. The design is then routed in Encounter. Since designer is the best judge of the circuit architecture, placement by the designer will allow achieve most optimal design. Several designs like IPCAM, issue logic, TLB, RF and Cache designs were carried out and the performance were compared against the fully custom and ASIC flow. The TLB, RF and Cache were the part of the HEMES microprocessor.
ContributorsMaurya, Satendra Kumar (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Vrudhula, Sarma (Committee member) / Allee, David (Committee member) / Arizona State University (Publisher)
Created2012
Description
Circuits on smaller technology nodes become more vulnerable to radiation-induced upset. Since this is a major problem for electronic circuits used in space applications, designers have a variety of solutions in hand. Radiation hardening by design (RHBD) is an approach, where electronic components are designed to work properly in certain radiation environments without the use of special fabrication processes. This work focuses on the cache design for a high performance microprocessor. The design tries to mitigate radiation effects like SEE, on a commercial foundry 45 nm SOI process. The design has been ported from a previously done cache design at the 90 nm process node. The cache design is a 16 KB, 4 way set associative, write-through design that uses a no-write allocate policy. The cache has been tested to write and read at above 2 GHz at VDD = 0.9 V. Interleaved layout, parity protection, dual redundancy, and checking circuits are used in the design to achieve radiation hardness. High speed is accomplished through the use of dynamic circuits and short wiring routes wherever possible. Gated clocks and optimized wire connections are used to reduce power. Structured methodology is used to build up the entire cache.
ContributorsXavier, Jerin (Author) / Clark, Lawrence T (Thesis advisor) / Cao, Yu (Committee member) / Allee, David R. (Committee member) / Arizona State University (Publisher)
Created2012
Description
Geology and its tangential studies, collectively known and referred to in this thesis as geosciences, have been paramount to the transformation and advancement of society, fundamentally changing the way we view, interact and live with the surrounding natural and built environment. It is important to recognize the value and importance of this interdisciplinary scientific field while reconciling its ties to imperial and colonizing extractive systems which have led to harmful and invasive endeavors. This intersection among geosciences, (environmental) justice studies, and decolonization is intended to promote inclusive pedagogical models through just and equitable methodologies and frameworks as to prevent further injustices and promote recognition and healing of old wounds. By utilizing decolonial frameworks and highlighting the voices of peoples from colonized and exploited landscapes, this annotated syllabus tackles the issues previously described while proposing solutions involving place-based education and the recentering of land within geoscience pedagogical models. (abstract)
ContributorsReed, Cameron E (Author) / Richter, Jennifer (Thesis director) / Semken, Steven (Committee member) / School of Earth and Space Exploration (Contributor, Contributor) / School of Sustainability (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
The ASU COVID-19 testing lab process was developed to operate as the primary testing site for all ASU staff, students, and specified external individuals. Tests are collected at various collection sites, including a walk-in site at the SDFC and various drive-up sites on campus; analysis is conducted on ASU campus and results are distributed virtually to all patients via the Health Services patient portal. The following is a literature review on past implementations of various process improvement techniques and how they can be applied to the ABCTL testing process to achieve laboratory goals. (abstract)
ContributorsKrell, Abby Elizabeth (Co-author) / Bruner, Ashley (Co-author) / Ramesh, Frankincense (Co-author) / Lewis, Gabriel (Co-author) / Barwey, Ishna (Co-author) / Myers, Jack (Co-author) / Hymer, William (Co-author) / Reagan, Sage (Co-author) / Compton, Carolyn (Thesis director) / McCarville, Daniel R. (Committee member) / Industrial, Systems & Operations Engineering Prgm (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
Clock generation and distribution are essential to CMOS microchips, providing synchronization to external devices and between internal sequential logic. Clocks in microprocessors are highly vulnerable to single event effects and designing reliable energy efficient clock networks for mission critical applications is a major challenge. This dissertation studies the basics of radiation hardening, essentials of clock design and impact of particle strikes on clocks in detail and presents design techniques for hardening complete clock systems in digital ICs.
Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse clocked latches and physical design methodologies for using TMR master-slave flip-flops in application specific ICs (ASICs) are proposed. A novel temporal pulse clocked latch design for low power radiation hardened applications is also proposed. Techniques for designing custom RHBD clock distribution networks (clock spines) and ASIC clock trees for a radiation hardened microprocessor using standard CAD tools are presented. A framework for analyzing the vulnerabilities of clock trees in general, and study the parameters that contribute the most to the tree’s failure, including impact on controlled latches is provided. This is then used to design an integrated temporally redundant clock tree and pulse clocked flip-flop based clocking scheme that is robust to single event transients (SETs) and single event upsets (SEUs). Subsequently, designing robust clock delay lines for use in double data rate (DDRx) memory applications is studied in detail. Several modules of the proposed radiation hardened all-digital delay locked loop are designed and studied. Many of the circuits proposed in this entire body of work have been implemented and tested on a standard low-power 90-nm process.
Since the sequential elements play a key role in deciding the robustness of any clocking strategy, hardened-by-design implementations of triple-mode redundant (TMR) pulse clocked latches and physical design methodologies for using TMR master-slave flip-flops in application specific ICs (ASICs) are proposed. A novel temporal pulse clocked latch design for low power radiation hardened applications is also proposed. Techniques for designing custom RHBD clock distribution networks (clock spines) and ASIC clock trees for a radiation hardened microprocessor using standard CAD tools are presented. A framework for analyzing the vulnerabilities of clock trees in general, and study the parameters that contribute the most to the tree’s failure, including impact on controlled latches is provided. This is then used to design an integrated temporally redundant clock tree and pulse clocked flip-flop based clocking scheme that is robust to single event transients (SETs) and single event upsets (SEUs). Subsequently, designing robust clock delay lines for use in double data rate (DDRx) memory applications is studied in detail. Several modules of the proposed radiation hardened all-digital delay locked loop are designed and studied. Many of the circuits proposed in this entire body of work have been implemented and tested on a standard low-power 90-nm process.
ContributorsChellappa, Srivatsan (Author) / Clark, Lawrence T (Thesis advisor) / Holbert, Keith E. (Committee member) / Cao, Yu (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2015
Description
For as long as humans have been working, they have been looking for ways to get that work done better, faster, and more efficient. Over the course of human history, mankind has created innumerable spectacular inventions, all with the goal of making the economy and daily life more efficient. Today, innovations and technological advancements are happening at a pace like never seen before, and technology like automation and artificial intelligence are poised to once again fundamentally alter the way people live and work in society. Whether society is prepared or not, robots are coming to replace human labor, and they are coming fast. In many areas artificial intelligence has disrupted entire industries of the economy. As people continue to make advancements in artificial intelligence, more industries will be disturbed, more jobs will be lost, and entirely new industries and professions will be created in their wake. The future of the economy and society will be determined by how humans adapt to the rapid innovations that are taking place every single day. In this paper I will examine the extent to which automation will take the place of human labor in the future, project the potential effect of automation to future unemployment, and what individuals and society will need to do to adapt to keep pace with rapidly advancing technology. I will also look at the history of automation in the economy. For centuries humans have been advancing technology to make their everyday work more productive and efficient, and for centuries this has forced humans to adapt to the modern technology through things like training and education. The thesis will additionally examine the ways in which the U.S. education system will have to adapt to meet the demands of the advancing economy, and how job retraining programs must be modernized to prepare workers for the changing economy.
ContributorsCunningham, Reed P. (Author) / DeSerpa, Allan (Thesis director) / Haglin, Brett (Committee member) / School of International Letters and Cultures (Contributor) / Department of Finance (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05
Description
Businesses stand to face many uncertainties from the moment they start up to every moment in between. A business can try to recognize them and plan ahead, react to them as they occur, or be rocked by a black swan they never saw coming. How a business deals with unforeseen events can increase its potential for success or failure. With this in mind, there is no better bridge between the here and now and the future than planning for change in order to move a company toward preparing for change, adapting to change and achieving optimal results. Interested in taking a step toward the digital age, Alpha Homes Management, Inc. (Alpha Homes) sought our help to explore ideas and options to take their company to a new level. This Barrett Creative Project was centered on designing a system for Alpha Homes that will replace their outdated paper-based system with a more digital one. This aligns with the project also featured as a capstone project as required by the information technology degree expectations. In supplement to the capstone, and for the Barrett Creative Project, the final product was presented to the owners of Alpha Homes Management, Inc. to be utilized by the business. The end goal is to provide a platform which provides a paperless environment for documentation and bring the company a step closer to having a robust internet presence. Now that the web-based application product has been created and presented, the testing phase can now begin to evaluate its efficacy.
ContributorsBrice-Nash, Tristan (Co-author) / Alfawzan, Mohammad (Co-author) / Doheny, Damien (Thesis director) / Rodriguez, Carlos (Committee member) / Information Technology (Contributor) / Barrett, The Honors College (Contributor)
Created2018-05