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Description
As the 3rd generation solar cell, quantum dot solar cells are expected to outperform the first 2 generations with higher efficiency and lower manufacture cost. Currently the main problems for QD cells are the low conversion efficiency and stability. This work is trying to improve the reliability as well as the device performance by inserting an interlayer between the metal cathode and the active layer. Titanium oxide and a novel nitrogen doped titanium oxide were compared and TiOxNy capped device shown a superior performance and stability to TiOx capped one. A unique light anneal effect on the interfacial layer was discovered first time and proved to be the trigger of the enhancement of both device reliability and efficiency. The efficiency was improved by 300% and the device can retain 73.1% of the efficiency with TiOxNy when normal device completely failed after kept for long time. Photoluminescence indicted an increased charge disassociation rate at TiOxNy interface. External quantum efficiency measurement also inferred a significant performance enhancement in TiOxNy capped device, which resulted in a higher photocurrent. X-ray photoelectron spectrometry was performed to explain the impact of light doping on optical band gap. Atomic force microscopy illustrated the effect of light anneal on quantum dot polymer surface. The particle size is increased and the surface composition is changed after irradiation. The mechanism for performance improvement via a TiOx based interlayer was discussed based on a trap filling model. Then Tunneling AFM was performed to further confirm the reliability of interlayer capped organic photovoltaic devices. As a powerful tool based on SPM technique, tunneling AFM was able to explain the reason for low efficiency in non-capped inverted organic photovoltaic devices. The local injection properties as well as the correspondent topography were compared in organic solar cells with or without TiOx interlayer. The current-voltage characteristics were also tested at a single interested point. A severe short-circuit was discovered in non capped devices and a slight reverse bias leakage current was also revealed in TiOx capped device though tunneling AFM results. The failure reason for low stability in normal devices was also discussed comparing to capped devices.
ContributorsYu, Jialin (Author) / Jabbour, Ghassan E. (Thesis advisor) / Alford, Terry L. (Thesis advisor) / Yu, Hongbin (Committee member) / Arizona State University (Publisher)
Created2011
ContributorsLovelady, Alexis (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-08
Description
Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.
ContributorsLiu, Tao (Author) / Bakkaloglu, Bertan (Thesis advisor) / Ozev, Sule (Committee member) / Vermeire, Bert (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2011
ContributorsAle, Lea (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-07
Description
Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.
ContributorsLiang, Hanshuang (Author) / Yu, Hongbin (Thesis advisor) / Ferry, David (Committee member) / Tracy, Clarence (Committee member) / Arizona State University (Publisher)
Created2011
Description
In this thesis, a Built-in Self Test (BiST) based testing solution is proposed to measure linear and non-linear impairments in the RF Transmitter path using analytical approach. Design issues and challenges with the impairments modeling and extraction in transmitter path are discussed. Transmitter is modeled for I/Q gain & phase mismatch, system non-linearity and DC offset using Matlab. BiST architecture includes a peak detector which includes a self mode mixer and 200 MHz filter. Self Mode mixing operation with filtering removes the high frequency signal contents and allows performing analysis on baseband frequency signals. Transmitter impairments were calculated using spectral analysis of output from the BiST circuitry using an analytical method. Matlab was used to simulate the system with known test impairments and impairment values from simulations were calculated based on system modeling in Mathematica. Simulated data is in good correlation with input test data along with very fast test time and high accuracy. The key contribution of the work is that, system impairments are extracted from transmitter response at baseband frequency using envelope detector hence eliminating the need of expensive high frequency ATE (Automated Test Equipments).
ContributorsGoyal, Nitin (Author) / Ozev, Sule (Thesis advisor) / Duman, Tolga (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and CPU performance counters and preemptively regulates supply voltage and frequency. System-level measurements from stateof-the-art commercial microprocessors are used to get workload, temperature and CPU performance counter values. The controller is designed and simulated using circuit-design and synthesis tools. At device-level, on-chip planar inductors suffer from low inductance occupying large chip area. On-chip inductors with integrated magnetic materials are designed, simulated and fabricated to explore performance-efficiency trade offs and explore potential applications such as resonant clocking and on-chip voltage regulation. A system level study is conducted to evaluate the effect of on-chip voltage regulator employing magnetic inductors as the output filter. It is concluded that neuromorphic power controller is beneficial for fine-grained per-core power management in conjunction with on-chip voltage regulators utilizing scaled magnetic inductors.
ContributorsSinha, Saurabh (Author) / Cao, Yu (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Yu, Hongbin (Committee member) / Christen, Jennifer B. (Committee member) / Arizona State University (Publisher)
Created2011
Description
The drive towards device scaling and large output power in millimeter and sub-millimeter wave power amplifiers results in a highly non-linear, out-of-equilibrium charge transport regime. Particle-based Full Band Monte Carlo device simulators allow an accurate description of this carrier dynamics at the nanoscale. This work initially compares GaN high electron mobility transistors (HEMTs) based on the established Ga-face technology and the emerging N-face technology, through a modeling approach that allows a fair comparison, indicating that the N-face devices exhibit improved performance with respect to Ga-face ones due to the natural back-barrier confinement that mitigates short-channel-effects. An investigation is then carried out on the minimum aspect ratio (i.e. gate length to gate-to-channel-distance ratio) that limits short channel effects in ultra-scaled GaN and InP HEMTs, indicating that this value in GaN devices is 15 while in InP devices is 7.5. This difference is believed to be related to the different dielectric properties of the two materials, and the corresponding different electric field distributions. The dielectric effects of the passivation layer in millimeter-wave, high-power GaN HEMTs are also investigated, finding that the effective gate length is increased by fringing capacitances, enhanced by the dielectrics in regions adjacent to the gate for layers thicker than 5 nm, strongly affecting the frequency performance of deep sub-micron devices. Lastly, efficient Full Band Monte Carlo particle-based device simulations of the large-signal performance of mm-wave transistor power amplifiers with high-Q matching networks are reported for the first time. In particular, a CellularMonte Carlo (CMC) code is self-consistently coupled with a Harmonic Balance (HB) frequency domain circuit solver. Due to the iterative nature of the HB algorithm, this simulation approach is possible only due to the computational efficiency of the CMC, which uses pre-computed scattering tables. On the other hand, HB allows the direct simulation of the steady-state behavior of circuits with long transient time. This work provides an accurate and efficient tool for the device early-stage design, which allows a computerbased performance evaluation in lieu of the extremely time-consuming and expensive iterations of prototyping and experimental large-signal characterization.
ContributorsGuerra, Diego (Author) / Saraniti, Marco (Thesis advisor) / Ferry, David K. (Committee member) / Goodnick, Stephen M (Committee member) / Ozev, Sule (Committee member) / Arizona State University (Publisher)
Created2011
ContributorsASU Library. Music Library (Publisher)
Created2018-04-09
ContributorsZhang, Ziyang (Performer) / Chen, Neilson (Performer) / ASU Library. Music Library (Publisher)
Created2018-04-12