Matching Items (2)
Description
Semiconductor nanowires are important candidates for highly scaled three dimensional electronic devices. It is very advantageous to combine their scaling capability with the high yield of planar CMOS technology by integrating nanowire devices into planar circuits. The purpose of this research is to identify the challenges associated with the fabrication of vertically oriented Si and Ge nanowire diodes and modeling their electrical behavior so that they can be utilized to create unique three dimensional architectures that can boost the scaling of electronic devices into the next generation. In this study, vertical Ge and Si nanowire Schottky diodes have been fabricated using bottom-up vapor-liquid-solid (VLS) and top-down reactive ion etching (RIE) approaches respectively. VLS growth yields nanowires with atomically smooth sidewalls at sub-50 nm diameters but suffers from the problem that the doping increases radially outwards from the core of the devices. RIE is much faster than VLS and does not suffer from the problem of non-uniform doping. However, it yields nanowires with rougher sidewalls and gets exceedingly inefficient in yielding vertical nanowires for diameters below 50 nm. The I-V characteristics of both Ge and Si nanowire diodes cannot be adequately fit by the thermionic emission model. Annealing in forming gas which passivates dangling bonds on the nanowire surface is shown to have a considerable impact on the current through the Si nanowire diodes indicating that fixed charges and traps on the surface of the devices play a major role in determining their electrical behavior. Also, due to the vertical geometry of the nanowire diodes, electric field lines originating from the metal and terminating on their sidewalls can directly modulate their conductivity. Both these effects have to be included in the model aimed at predicting the current through vertical nanowire diodes. This study shows that the current through vertical nanowire diodes cannot be predicted accurately using the thermionic emission model which is suitable for planar devices and identifies the factors needed to build a comprehensive analytical model for predicting the current through vertically oriented nanowire diodes.
ContributorsChandra, Nishant (Author) / Goodnick, Stephen M (Thesis advisor) / Tracy, Clarence J. (Committee member) / Yu, Hongbin (Committee member) / Ferry, David K. (Committee member) / Arizona State University (Publisher)
Created2014
Description
Layers of intrinsic hydrogenated amorphous silicon and amorphous silicon carbide
were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and FTIR spectra were observed at incremental stages of thermal annealing. By observing the changes in the lifetimes the sample structure responsible for the most thermally robust surface passivation could be determined. These results were correlated to the optical band gap and the position and relative area of peaks in the FTIR spectra related to to silicon-hydrogen bonds in the layers. It was found that due to an increased presence of hydrogen bonded to silicon at voids within the passivating layer, hydrogenated amorphous silicon carbide at the interface of the substrate coupled with a hydrogenated amorphous silicon top layer provides better passivation after high temperature annealing than other device structures.
were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and FTIR spectra were observed at incremental stages of thermal annealing. By observing the changes in the lifetimes the sample structure responsible for the most thermally robust surface passivation could be determined. These results were correlated to the optical band gap and the position and relative area of peaks in the FTIR spectra related to to silicon-hydrogen bonds in the layers. It was found that due to an increased presence of hydrogen bonded to silicon at voids within the passivating layer, hydrogenated amorphous silicon carbide at the interface of the substrate coupled with a hydrogenated amorphous silicon top layer provides better passivation after high temperature annealing than other device structures.
ContributorsJackson, Alec James (Author) / Holman, Zachary (Thesis advisor) / Bertoni, Mariana (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2016