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- Creators: Arizona State University
- Creators: Bertoni, Mariana
- Creators: Summers, Nicholas, M.S
Description
Silicon carbide (SiC), long touted as a material that can satisfy the specific property requirements for high temperature and high power applications, was studied quantitatively using various techniques. The electronic band structure of 4H SiC is examined in the first half of this dissertation. A brief introduction to band structure calculations, with particular emphasis on the empirical pseudopotential method, is given as a foundation for the subsequent work. Next, the crystal pseudopotential for 4H SiC is derived in detail, and a novel approach using a genetic algorithm search routine is employed to find the fitting parameters needed to generate the band structure. Using this technique, the band structure is fitted to experimentally measured energy band gaps giving an indirect band gap energy of 3.28 eV, and direct f¡, M, K and L energy transitions of 6.30, 4.42, 7.90 and 6.03 eV, respectively. The generated result is also shown to give effective mass values of mMf¡*=0.66m0, mMK*=0.31m0, mML*=0.34m0, in close agreement with experimental results. The second half of this dissertation discusses computational work in finding the electron Hall mobility and Hall scattering factor for 6H SiC. This disscussion begins with an introductory chapter that gives background on how scattering rates are dervied and the specific expressions for important mechanisms. The next chapter discusses mobility calculations for 6H SiC in particular, beginnning with Rode's method to solve the Boltzmann transport equation. Using this method and the transition rates of the previous chapter, an acoustic deformation potential DA value of 5.5 eV, an inter-valley phonon deformation potential Dif value of 1.25~1011 eV/m and inter-valley phonon energy ℏfÖif of 65 meV that simultaneously fit experimental data on electron Hall mobility and Hall scattering factor was found.
ContributorsNg, Garrick (Author) / Schroder, Dieter K. (Thesis advisor) / Vasileska, Dragica (Committee member) / Skromme, Brian (Committee member) / Alford, Terry (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2010
Description
Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250°C.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235°C.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
ContributorsSummers, Nicholas, M.S (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010
Description
Layers of intrinsic hydrogenated amorphous silicon and amorphous silicon carbide
were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and FTIR spectra were observed at incremental stages of thermal annealing. By observing the changes in the lifetimes the sample structure responsible for the most thermally robust surface passivation could be determined. These results were correlated to the optical band gap and the position and relative area of peaks in the FTIR spectra related to to silicon-hydrogen bonds in the layers. It was found that due to an increased presence of hydrogen bonded to silicon at voids within the passivating layer, hydrogenated amorphous silicon carbide at the interface of the substrate coupled with a hydrogenated amorphous silicon top layer provides better passivation after high temperature annealing than other device structures.
were prepared on a polished, intrinsic crystalline silicon substrate via plasma-enhanced chemical vapor deposition to simulate heterojunction device relevant stacks of various materials. The minority carrier lifetime, optical band gap and FTIR spectra were observed at incremental stages of thermal annealing. By observing the changes in the lifetimes the sample structure responsible for the most thermally robust surface passivation could be determined. These results were correlated to the optical band gap and the position and relative area of peaks in the FTIR spectra related to to silicon-hydrogen bonds in the layers. It was found that due to an increased presence of hydrogen bonded to silicon at voids within the passivating layer, hydrogenated amorphous silicon carbide at the interface of the substrate coupled with a hydrogenated amorphous silicon top layer provides better passivation after high temperature annealing than other device structures.
ContributorsJackson, Alec James (Author) / Holman, Zachary (Thesis advisor) / Bertoni, Mariana (Committee member) / Kozicki, Michael (Committee member) / Arizona State University (Publisher)
Created2016