Matching Items (6)
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- All Subjects: pmc
- All Subjects: RRAM
- Creators: Barnaby, Hugh
Description
Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in situ, via the application of a bias on laterally placed electrodes, creates a large number of promising applications. A novel PMC-based lateral microwave switch was fabricated and characterized for use in microwave systems. It has demonstrated low insertion loss, high isolation, low voltage operation, low power and low energy consumption, and excellent linearity. Due to its non-volatile nature the switch operates with fewer biases and its simple planar geometry makes possible innovative device structures which can be potentially integrated into microwave power distribution circuits. PMC technology is also used to develop lateral dendritic metal electrodes. A lateral metallic dendritic network can be grown in a solid electrolyte (GeSe) or electrodeposited on SiO2 or Si using a water-mediated method. These dendritic electrodes grown in a solid electrolyte (GeSe) can be used to lower resistances for applications like self-healing interconnects despite its relatively low light transparency; while the dendritic electrodes grown using water-mediated method can be potentially integrated into solar cell applications, like replacing conventional Ag screen-printed top electrodes as they not only reduce resistances but also are highly transparent. This research effort also laid a solid foundation for developing dendritic plasmonic structures. A PMC-based lateral dendritic plasmonic structure is a device that has metallic dendritic networks grown electrochemically on SiO2 with a thin layer of surface metal nanoparticles in liquid electrolyte. These structures increase the distribution of particle sizes by connecting pre-deposited Ag nanoparticles into fractal structures and result in three significant effects, resonance red-shift, resonance broadening and resonance enhancement, on surface plasmon resonance for light trapping simultaneously, which can potentially enhance thin film solar cells' performance at longer wavelengths.
ContributorsRen, Minghan (Author) / Kozicki, Michael (Thesis advisor) / Schroder, Dieter (Committee member) / Roedel, Ronald (Committee member) / Barnaby, Hugh (Committee member) / Arizona State University (Publisher)
Created2011
Description
Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration with the CMOS back end of line (BEOL) process flow. One area where detailed study is lacking is the reliability of PMC devices. In previous reliability work, the low and high resistance states were monitored for periods of hours to days without any applied voltage and the results were extrapolated to several years (>10) but little has been done to analyze the low resistance state under stress. With or without stress, the low resistance state appears to be highly stable but a gradual increase in resistance with time, less than one order of magnitude after ten years when extrapolated, has been observed. It is important to understand the physics behind this resistance rise mechanism to comprehend the reliability issues associated with the low resistance state. This is also related to the erase process in PMC cells where the transition from the ON to OFF state occurs under a negative voltage. Hence it is important to investigate this erase process in PMC cells under different conditions and to model it. Analyzing the programming and the erase operations separately is important for any memory technology but its ability to cycle efficiently (reliably) at low voltages and for more than 1E4 cycles (without affecting the cells performance) is more critical. Future memory technologies must operate with the low power supply voltages (<1V) required for small geometry nodes. Low voltage programming of PMC memory devices has previously been demonstrated using slow voltage sweeps and small numbers of fast pulses. In this work PMC memory cells were cycled at low voltages using symmetric pulses with different load resistances and the distribution of the ON and OFF resistances was analyzed. The effect of the program current used during the program-erase cycling on the resulting resistance distributions is also investigated. Finally the variation found in the behavior of similar resistance ON states in PMC cells was analyzed more in detail and measures to reduce this variation were looked into. It was found that slow low current programming helped reducing the variation in erase times of similar resistance ON states in PMC cells. This scheme was also used as a pre-conditioning technique and the improvements in subsequent cycling behavior were compared.
ContributorsKamalanathan, Deepak (Author) / Kozicki, Dr. Michael (Thesis advisor) / Schroder, Dr. Dieter (Committee member) / Goryll, Dr. Michael (Committee member) / Alford, Dr. Terry (Committee member) / Arizona State University (Publisher)
Created2011
Description
This thesis outlines the hand-held memory characterization testing system that is to be created into a PCB (printed circuit board). The circuit is designed to apply voltages diagonally through a RRAM cell (32x32 memory array). The purpose of this sweep across the RRAM is to measure and calculate the high and low resistance state value over a specified amount of testing cycles. With each cell having a unique output of high and low resistance states a unique characterization of each RRAM cell is able to be developed. Once the memory is characterized, the specific RRAM cell that was tested is then able to be used in a varying amount of applications for different things based on its uniqueness. Due to an inability to procure a packaged RRAM cell, a Mock-RRAM was instead designed in order to emulate the same behavior found in a RRAM cell.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
The final testing circuit and Mock-RRAM are varied and complex but come together to be able to produce a measured value of the high resistance and low resistance state. This is done by the Arduino autonomously digitizing the anode voltage, cathode voltage, and output voltage. A ramp voltage that sweeps from 1V to -1V is applied to the Mock-RRAM acting as an input. This ramp voltage is then later defined as the anode voltage which is just one of the two nodes connected to the Mock-RRAM. The cathode voltage is defined as the other node at which the voltage drops across the Mock-RRAM. Using these three voltages as input to the Arduino, the Mock-RRAM path resistance is able to be calculated at any given point in time. Conducting many test cycles and calculating the high and low resistance values allows for a graph to be developed of the chaotic variation of resistance state values over time. This chaotic variation can then be analyzed further in the future in order to better predict trends and characterize the RRAM cell that was tested.
Furthermore, the interchangeability of many devices on the PCB allows for the testing system to do more in the future. Ports have been added to the final PCB in order to connect a packaged RRAM cell. This will allow for the characterization of a real RRAM memory cell later down the line rather than a Mock-RRAM as emulation. Due to the autonomous testing, very few human intervention is needed which makes this board a great baseline for others in the future looking to add to it and collect larger pools of data.
ContributorsDobrin, Ryan Christopher (Co-author) / Halden, Matthew (Co-author) / Hall, Tanner (Co-author) / Barnaby, Hugh (Thesis director) / Kitchen, Jennifer (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2019-05
Description
Most machine learning algorithms, and specifically neural networks, utilize vector-matrix multiplication (VMM) to process information, but these calculations are CPU intensive and can have long run-times. This issue is fundamentally outlined by the von Neumann bottleneck. Because of this undesirable expense associated with performing VMM via software, the exploration of new ways to perform the same calculations via hardware have grown more popular. When performed with hardware that is specialized to perform these calculations, VMM becomes far more power-efficient and less time consuming. This project expands upon those principles and seeks to validate the use of RRAM in this hardware.
The flexibility of the conductance of RRAM makes these devices a strong contender for hardware-driven VMM calculation for neural network computing. The conductance of these devices is affected by the pulse width of a voltage signal sent across the devices at each node. This pulse is produced on-chip and can be modified by user inputs. The design of this pulse- producing circuit, as well as the simulated and physical functionality of the design, is discussed in this Honors Thesis.
Simulation and physical testing of the pulse-producing design on the ASIC have verified correct operation of the design. This operation is imperative to the future ability of the ASIC to perform accurate VMM.
ContributorsPearson, Katherine (Author) / Barnaby, Hugh (Thesis director) / Wilson, Donald (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor) / School of International Letters and Cultures (Contributor)
Created2022-05
Description
The formation of dendrites in materials is usually seen as a failure-inducing defect in devices. Naturally, most research views dendrites as a problem needing a solution while focusing on process control techniques and post-mortem analysis of various stress patterns with the ultimate goal of total suppression of the structures. However, programmable metallization cell (PMC) technology embraces dendrite formation in chalcogenide glasses by utilizing the nascent conductive filaments as its core operative element. Furthermore, exciting More-than-Moore capabilities in the realms of device watermarking and hardware encryption schema are made possible by the random nature of dendritic branch growth. While dendritic structures have been observed and are well-documented in solid state materials, there is still no satisfactory theoretical model that can provide insight and a better understanding of how dendrites form. Ultimately, what is desired is the capability to predict the final structure of the conductive filament in a PMC device so that exciting new applications can be developed with PMC technology.
This thesis details the results of an effort to create a first-principles MATLAB simulation model that uses configurable physical parameters to generate images of dendritic structures. Generated images are compared against real-world samples. While growth has a significant random component, there are several reliable characteristics that form under similar parameter sets that can be monitored such as the relative length of major dendrite arms, common branching angles, and overall growth directionality.
The first simulation model that was constructed takes a Newtonian perspective of the problem and is implemented using the Euler numerical method. This model has several shortcomings stemming majorly from the simplistic treatment of the problem, but is highly performant. The model is then revised to use the Verlet numerical method, which increases the simulation accuracy, but still does not fully resolve the issues with the theoretical background. The final simulation model returns to the Euler method, but is a stochastic model based on Mott-Gurney’s ion hopping theory applied to solids. The results from this model are seen to match real samples the closest of all simulations.
This thesis details the results of an effort to create a first-principles MATLAB simulation model that uses configurable physical parameters to generate images of dendritic structures. Generated images are compared against real-world samples. While growth has a significant random component, there are several reliable characteristics that form under similar parameter sets that can be monitored such as the relative length of major dendrite arms, common branching angles, and overall growth directionality.
The first simulation model that was constructed takes a Newtonian perspective of the problem and is implemented using the Euler numerical method. This model has several shortcomings stemming majorly from the simplistic treatment of the problem, but is highly performant. The model is then revised to use the Verlet numerical method, which increases the simulation accuracy, but still does not fully resolve the issues with the theoretical background. The final simulation model returns to the Euler method, but is a stochastic model based on Mott-Gurney’s ion hopping theory applied to solids. The results from this model are seen to match real samples the closest of all simulations.
ContributorsFoss, Ryan (Author) / Kozicki, Michael N (Thesis advisor) / Barnaby, Hugh (Committee member) / Allee, David R. (Committee member) / Arizona State University (Publisher)
Created2016
Description
Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization.
To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.
The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.
The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.
To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities.
The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior.
The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.
ContributorsRajabi, Saba (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2014