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Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon

There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
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Description
Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3

Carrier lifetime is one of the few parameters which can give information about the low defect densities in today's semiconductors. In principle there is no lower limit to the defect density determined by lifetime measurements. No other technique can easily detect defect densities as low as 10-9 - 10-10 cm-3 in a simple, contactless room temperature measurement. However in practice, recombination lifetime τr measurements such as photoconductance decay (PCD) and surface photovoltage (SPV) that are widely used for characterization of bulk wafers face serious limitations when applied to thin epitaxial layers, where the layer thickness is smaller than the minority carrier diffusion length Ln. Other methods such as microwave photoconductance decay (µ-PCD), photoluminescence (PL), and frequency-dependent SPV, where the generated excess carriers are confined to the epitaxial layer width by using short excitation wavelengths, require complicated configuration and extensive surface passivation processes that make them time-consuming and not suitable for process screening purposes. Generation lifetime τg, typically measured with pulsed MOS capacitors (MOS-C) as test structures, has been shown to be an eminently suitable technique for characterization of thin epitaxial layers. It is for these reasons that the IC community, largely concerned with unipolar MOS devices, uses lifetime measurements as a "process cleanliness monitor." However when dealing with ultraclean epitaxial wafers, the classic MOS-C technique measures an effective generation lifetime τg eff which is dominated by the surface generation and hence cannot be used for screening impurity densities. I have developed a modified pulsed MOS technique for measuring generation lifetime in ultraclean thin p/p+ epitaxial layers which can be used to detect metallic impurities with densities as low as 10-10 cm-3. The widely used classic version has been shown to be unable to effectively detect such low impurity densities due to the domination of surface generation; whereas, the modified version can be used suitably as a metallic impurity density monitoring tool for such cases.
ContributorsElhami Khorasani, Arash (Author) / Alford, Terry (Thesis advisor) / Goryll, Michael (Committee member) / Bertoni, Mariana (Committee member) / Arizona State University (Publisher)
Created2013
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Description
Photodetectors in the 1.7 to 4.0 μm range are being commercially developed on InP substrates to meet the needs of longer wavelength applications such as thermal and medical sensing. Currently, these devices utilize high indium content metamorphic Ga1-xInxAs (x > 0.53) layers to extend the wavelength range beyond the 1.7

Photodetectors in the 1.7 to 4.0 μm range are being commercially developed on InP substrates to meet the needs of longer wavelength applications such as thermal and medical sensing. Currently, these devices utilize high indium content metamorphic Ga1-xInxAs (x > 0.53) layers to extend the wavelength range beyond the 1.7 μm achievable using lattice matched GaInAs. The large lattice mismatch required to reach the extended wavelengths results in photodetector materials that contain a large number of misfit dislocations. The low quality of these materials results in a large nonradiative Shockley Read Hall generation/recombination rate that is manifested as an undesirable large thermal noise level in these photodetectors. This work focuses on utilizing the different band structure engineering methods to design more efficient devices on InP substrates. One prospective way to improve photodetector performance at the extended wavelengths is to utilize lattice matched GaInAs/GaAsSb structures that have a type-II band alignment, where the ground state transition energy of the superlattice is smaller than the bandgap of either constituent material. Over the extended wavelength range of 2 to 3 μm this superlattice structure has an optimal period thickness of 3.4 to 5.2 nm and a wavefunction overlap of 0.8 to 0.4, respectively. In using a type-II superlattice to extend the cutoff wavelength there is a tradeoff between the wavelength reached and the electron-hole wavefunction overlap realized, and hence absorption coefficient achieved. This tradeoff and the subsequent reduction in performance can be overcome by two methods: adding bismuth to this type-II material system; applying strain on both layers in the system to attain strain-balanced condition. These allow the valance band alignment and hence the wavefunction overlap to be tuned independently of the wavelength cutoff. Adding 3% bismuth to the GaInAs constituent material, the resulting lattice matched Ga0.516In0.484As0.970Bi0.030/GaAs0.511Sb0.489superlattice realizes a 50% larger absorption coefficient. While as, similar results can be achieved with strain-balanced condition with strain limited to 1.9% on either layer. The optimal design rules derived from the different possibilities make it feasible to extract superlattice period thickness with the best absorption coefficient for any cutoff wavelength in the range.  
ContributorsSharma, Ankur R (Author) / Johnson, Shane (Thesis advisor) / Goryll, Michael (Committee member) / Roedel, Ronald (Committee member) / Arizona State University (Publisher)
Created2013
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Description
The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an

The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an extremely cost effective way. Higher integration leads to electronics with increased functionality and a smaller finished product. The MESFETs are designed in-house by the research group led by Dr. Trevor Thornton. The layouts are then sent to multi-project wafer (MPW) integrated circuit foundry companies, such as the Metal Oxide Semiconductor Implementation Service (MOSIS) to be fabricated. Once returned, the electrical characteristics of the devices are measured. The MESFET has been implemented in various applications by the research group, including the low dropout linear regulator (LDO) and RF power amplifier. An advantage of the MESFET is that it can function in extreme environments such as space, allowing for complex electrical systems to continue functioning properly where traditional transistors would fail.
ContributorsKam, Jason (Author) / Thornton, Trevor (Thesis director) / Goryll, Michael (Committee member) / Barrett, The Honors College (Contributor) / Electrical Engineering Program (Contributor)
Created2015-05
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Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the

The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
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Description
Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals

Silicon Carbide (SiC) junction field effect transistors (JFETs) are ideal for switching high current, high voltage loads in high temperature environments. These devices require external drive circuits to generate pulse width modulated (PWM) signals switching from 0V to approximately 10V. Advanced CMOS microcontrollers are ideal for generating the PWM signals but are limited in output voltage due to their low breakdown voltage within the CMOS drive circuits. As a result, an intermediate buffer stage is required between the CMOS circuitry and the JFET. In this thesis, a discrete silicon-on-insulator (SOI) metal semiconductor field effect transistor (MESFET) was used to drive the gate of a SiC power JFET switching a 120V RMS AC supply into a 30Ω load. The wide operating temperature range and high breakdown voltage of up to 50V make the SOI MESFET ideal for power electronics in extreme environments. Characteristic curves for the MESFET were measured up to 250&degC.; To drive the JFET, the MESFET was DC biased and then driven by a 1.2V square wave PWM signal to switch the JFET gate from 0 to 10V at frequencies up to 20kHz. For simplicity, the 1.2V PWM square wave signal was provided by a 555 timer. The JFET gate drive circuit was measured at high temperatures up to 235&degC.; The circuit operated well at the high temperatures without any damage to the SOI MESFET or SiC JFET. The drive current of the JFET was limited by the duty cycle range of the 555 timer used. The SiC JFET drain current decreased with increased temperature. Due to the easy integration of MESFETs into SOI CMOS processes, MESFETs can be fabricated alongside MOSFETs without any changes in the process flow. This thesis demonstrates the feasibility of integrating a MESFET with CMOS PWM circuitry for a completely integrated SiC driver thus eliminating the need for the intermediate buffer stage.
ContributorsSummers, Nicholas, M.S (Author) / Thornton, Trevor J (Thesis advisor) / Goryll, Michael (Committee member) / Schroder, Dieter (Committee member) / Arizona State University (Publisher)
Created2010
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Description
InAsBi is a narrow direct gap III-V semiconductor that has recently attracted considerable attention because its bandgap is tunable over a wide range of mid- and long-wave infrared wavelengths for optoelectronic applications. Furthermore, InAsBi can be integrated with other III-V materials and is potentially an alternative to commercial II-VI

InAsBi is a narrow direct gap III-V semiconductor that has recently attracted considerable attention because its bandgap is tunable over a wide range of mid- and long-wave infrared wavelengths for optoelectronic applications. Furthermore, InAsBi can be integrated with other III-V materials and is potentially an alternative to commercial II-VI photodetector materials such as HgCdTe.

Several 1 μm thick, nearly lattice-matched InAsBi layers grown on GaSb are examined using Rutherford backscattering spectrometry and X-ray diffraction. Random Rutherford backscattering measurements indicate that the average Bi mole fraction ranges from 0.0503 to 0.0645 for the sample set, and ion channeling measurements indicate that the Bi atoms are substitutional. The X-ray diffraction measurements show a diffraction sideband near the main (004) diffraction peak, indicating that the Bi mole fraction is not laterally uniform in the layer. The average out of plane tetragonal distortion is determined by modeling the main and sideband diffraction peaks, from which the average unstrained lattice constant of each sample is determined. By comparing the Bi mole fraction measured by random Rutherford backscattering with the InAsBi lattice constant for the sample set, the lattice constant of zinc blende InBi is determined to be 6.6107 Å.

Several InAsBi quantum wells tensilely strained to the GaSb lattice constant with dilute quantities of Bi are characterized using photoluminescence spectroscopy. Investigation of the integrated intensity as a function of carrier excitation density spanning 5×1025 to 5×1026 cm-3 s-1 indicates radiative dominated recombination and high quantum efficiency over the 12 to 250 K temperature range. The bandgap of InAsBi is ascertained from the photoluminescence spectra and parameterized as a function of temperature using the Einstein single oscillator model. The dilute Bi mole fraction of the InAsBi quantum wells is determined by comparing the measured bandgap energy to that predicted by the valence band anticrossing model. The Bi mole fraction determined by photoluminescence agrees reasonably well with that estimated using secondary ion mass spectrometry.
ContributorsShalindar Christraj, Arvind Joshua Jaydev (Author) / Johnson, Shane R (Thesis advisor) / Alford, Terry L. (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2016
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Description
The molecular beam epitaxy growth of the III-V semiconductor alloy indium arsenide antimonide bismide (InAsSbBi) is investigated over a range of growth temperatures and V/III flux ratios. Bulk and quantum well structures grown on gallium antimonide (GaSb) substrates are examined. The relationships between Bi incorporation, surface morphology, growth temperature, and

The molecular beam epitaxy growth of the III-V semiconductor alloy indium arsenide antimonide bismide (InAsSbBi) is investigated over a range of growth temperatures and V/III flux ratios. Bulk and quantum well structures grown on gallium antimonide (GaSb) substrates are examined. The relationships between Bi incorporation, surface morphology, growth temperature, and group-V flux are explored. A growth model is developed based on the kinetics of atomic desorption, incorporation, surface accumulation, and droplet formation. The model is applied to InAsSbBi, where the various process are fit to the Bi, Sb, and As mole fractions. The model predicts a Bi incorporation limit for lattice matched InAsSbBi grown on GaSb.The optical performance and bandgap energy of InAsSbBi is examined using photoluminescence spectroscopy. Emission is observed from low to room temperature with peaks ranging from 3.7 to 4.6 μm. The bandgap as function of temperature is determined from the first derivative maxima of the spectra fit to an Einstein single oscillator model. The photoluminescence spectra is observed to significantly broaden with Bi content as a result of lateral composition variations and the highly mismatched nature of Bi atoms, pairs, and clusters in the group-V sublattice.
A bowing model is developed for the bandgap and band offsets of the quinary alloy GaInAsSbBi and its quaternary constituents InAsSbBi and GaAsSbBi. The band anticrossing interaction due to the highly mismatched Bi atoms is incorporated into the relevant bowing terms. An algorithm is developed for the design of mid infrared GaInAsSbBi
quantum wells, with three degrees freedom to independently tune transition energy, in plane strain, and band edge offsets for desired electron and hole confinement.
The physical characteristics of the fundamental absorption edge of the relevant III-V binaries GaAs, GaSb, InAs, and InSb are examined using spectroscopic ellipsometry. A five parameter model is developed that describes the key physical characteristics of the absorption edge, including the bandgap energy, the Urbach tail, and the absorption coefficient at the bandgap.
The quantum efficiency and recombination lifetimes of bulk InAs0.911Sb0.089 grown by molecular beam epitaxy is investigated using excitation and temperature dependent steady state photoluminescence. The Shockley-Read-Hall, radiative, and Auger recombination lifetimes are determined.
ContributorsSchaefer, Stephen Thomas (Author) / Johnson, Shane R (Thesis advisor) / Zhang, Yong-Hang (Committee member) / Goryll, Michael (Committee member) / King, Richard (Committee member) / Arizona State University (Publisher)
Created2020