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Description
DC-DC converters are widely employed to interface one voltage level with another through step-up or step-down operation. In recent years, step-up DC-DC converters have been a key component in harnessing energy through renewable sources by providing an interface to integrate low voltage systems to DC-AC converters or microgrids. They find increasing applications in battery and fuel cell electric vehicles which can benefit from high and variable DC link voltage. It is important to optimize these converters for higher efficiency while achieving high gain and high power density. Non-isolated DC-DC converters are an attractive option due to the reduced complexity of magnetic design, smaller size, and lower cost. However, in these topologies, achieving a very high gain along with high efficiency has been a challenge. This work encompasses different non-isolated high gain DC-DC converters for electric vehicle and renewable energy applications. The converter topologies proposed in this work can easily achieve a conversion ratio above 20 with lower voltage and current stress across devices. For applications requiring wide input or output voltage range, different control schemes, as well as modified converter configurations, are proposed. Moreover, the converter performance is optimized by employing wide band-gap devices-based hardware prototypes. It enables higher switching frequency operation with lower switching losses. In recent times, multiple soft-switching techniques have been introduced which enable higher switching frequency operation by minimizing the switching loss. This work also discusses different soft-switching mechanisms for the high conversion ratio converter and the proposed mechanism improves the converter efficiency significantly while reducing the inductor size. Further, a novel electric vehicle traction architecture with low voltage battery and multi-input high gain DC-DC converter is introduced in this work. The proposed architecture with multiple 48 V battery packs and integrated, multi-input, high conversion ratio DC-DC converters, can reduce the maximum voltage in the vehicle during emergencies to 48 V, mitigate cell balancing issues in battery, and provide a wide variable DC link voltage. The implementation of high conversion ratio converter in multiple configurations for the proposed architecture has been discussed in detail and the proposed converter operation is validated experimentally through a scaled hardware prototype.
ContributorsGupta, Ankul (Author) / Ayyanar, Raja (Thesis advisor) / Lei, Qin (Committee member) / Bakkaloglu, Bertan (Committee member) / Ranjram, Mike (Committee member) / Arizona State University (Publisher)
Created2022
Description
Although the increasing penetration of electric vehicles (EVs) has reduced the emissionof the greenhouse gas caused by vehicles, it would lead to serious congestion
on-road and in charging stations. Strategic coordination of EV charging would benefit
the transportation system. However, it is difficult to model a congestion game,
which includes choosing charging routes and stations. Furthermore, conventional algorithms
cannot balance System Optimization and User Equilibrium, which can cause
a huge waste to the whole society. To solve these problems, this paper shows (1) a
congestion game setup to optimize and reveal the relationship between EV users,
(2) using ε – Nash Equilibrium to reduce the inefficient impact from the self-minded
the behavior of the EV users, and (3) finding the relatively optimal solution to approach
Pareto-Optimal solution. The proposed method can reduce more total EVs charging
time and most EV users’ charging time than existing methods. Numerical simulations
demonstrate the advantages of the new method compared to the current methods.
ContributorsYu, Hao (Author) / Weng, Yang (Thesis advisor) / Yu, Hongbin (Committee member) / Zhang, Yanchao (Committee member) / Arizona State University (Publisher)
Created2022
Description
Increased demand on bandwidth has resulted in wireless communications and radar systems sharing spectrum. As signal transmissions from both modalities coexist, methodologies must be designed to reduce the induced interference from each system. This work considers the problem of tracking an object using radar measurements embedded in noise and corrupted from transmissions of multiple communications users. Radar received signals in low noise can be successively processed to estimate object parameters maximum likelihood estimation. For linear frequency-modulated (LFM) signals, such estimates can be efficiently computed by integrating the Wigner distribution along lines in the time-frequency (TF) plane. However, the presence of communications interference highly reduces estimation performance.This thesis proposes a new approach to increase radar estimation performance by integrating a highly-localized TF method with data clustering. The received signal is first decomposed into highly localized Gaussians using the iterative matching pursuit decomposition (MPD). As the MPD is iterative, high noise levels can be reduced by appropriately selecting the algorithm’s stopping criteria. The decomposition also provides feature vectors of reduced dimensionality that can be used for clustering using a Gaussian mixture model (GMM). The proposed estimation method integrates along lines of a modified Wigner distribution of the Gaussian clusters in the TF plane. Using simulations, the object parameter estimation performance of the MPD is shown to highly improve when the MPD is integrated with GMM clustering.
ContributorsZhang, Yiming (Author) / Papandreou-Suppappola, Antonia (Thesis advisor) / Moraffah, Bahman (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Arizona State University (Publisher)
Created2022
Description
Many of the advanced integrated circuits in the past used monolithic grade die due to power, performance and cost considerations. Today, heterogenous integration of multiple dies into a single package is possible because of the advancement in packaging. These heterogeneous multi-chiplet systems provide high performance at minimum fabrication cost. The main challenge is to interconnect these chiplets while keeping the power and performance closer to monolithic grade. Intel’s Advanced Interface Bus (AIB) is a short reach interface that offers high bandwidth, power efficient, low latency, and cost effective on-package connectivity between chiplets. It supports flexible interconnection of the chiplets with high speed data transfer. Specifically, it is a die to die parallel interface implemented with multiple configurable channels, routed between micro-bumps. In this work, the AIB model is synthesized in 65nm technology node and a performancemodel is generated. This model generates area, power and latency results for multiple technology nodes using technology scaling methods. For all nodes, the area, power and latency values increase linearly with frequency and number of channels. The bandwidth also increases linearly with the number of input/output lanes, which is a function of the micro-bump pitch. Next, the AIB performance model is integrated with the benchmarking simulator, Scalable In-Memory Acceleration With Mesh (SIAM), to realize a scalable chipletbased end-to-end system. The Ground-Referenced Signaling (GRS) driver model in SIAM is replaced with the AIB model and an end-to-end evaluation of Deep Neural Network (DNN) performance is carried out for two contemporary DNN models. Comparative analysis between SIAM with GRS and SIAM with AIB show that while the area of AIB transmitter is less compared to GRS transmitter, the AIB transmitter offers higher bandwidth than GRS transmitter at the expense of higher energy. Furthermore, SIAM with AIB provides more realistic timing numbers since the NoP driver latency is also taken into consideration.
ContributorsCHERIAN, NINOO SUSAN (Author) / Chakrabarti, Chaitali (Thesis advisor) / Cao, Yu (Committee member) / Fan, Deliang (Committee member) / Arizona State University (Publisher)
Created2022
Description
The strong demand for the advancing of Moore’s law on device size scaling down has accelerated the miniaturization of passive devices. Among these important electronic components, inductors are facing challenges because the inductance value, which is strongly dependent on the coil number for the air core inductor case, will be sacrificed when the size is shrinking. Adding magnetic core is one of the solutions due to its enhancement of inductance density but it will also add complexity to the fabrication process, and the core loss induced by the eddy current at high frequency is another drawback. In this report, the output of this research will be presented, which has three parts. In the first part, the CoZrTaB thin films are sputtered on different substrates and characterized comprehensively. The laminated CoZrTaB thin films have been also investigated, showing low coercivity and anisotropy field on both Si and polyimide substrates. Also, the different process conditions that could affect the magnetic properties are investigated.
In the second part, Ansys Maxwell software is used to optimize the lamination profile and the magnetic core inductor structure. The measured M-H loop is imported to improve the simulation accuracy.
In the third part, a novel method to fabricate the magnetic core inductors on flexible substrates is proposed. The sandwich magnetic core inductor is fabricated and assembled with flipchip bonder. The measurement result shows that this single-turn magnetic core inductor can achieve up to 24% inductance enhancement and quality factor of 7.42. The super low DC resistance (< 60 mΩ) proves that it is a good candidate to act as the passive component in the power delivery module and the use of polyimide-based substrate extends its compatibility to more packaging form factors.
ContributorsWu, Yanze (Author) / Yu, Hongbin (Thesis advisor) / Chickamenahalli, Shamala (Committee member) / Rizzo, Nicholas (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022
Description
The Deep Neural Network (DNN) is one type of a neuromorphic computing approach that has gained substantial interest today. To achieve continuous improvement in accuracy, the depth, and the size of the deep neural network needs to significantly increase. As the scale of the neural network increases, it poses a severe challenge to its hardware implementation with conventional Computer Processing Unit (CPU) and Graphic Processing Unit (GPU) from the perspective of power, computation, and memory. To address this challenge, domain specific specialized digital neural network accelerators based on Field Programmable Gate Array (FPGAs) and Application Specific Integrated Circuits (ASICs) have been developed. However, limitations still exist in terms of on-chip memory capacity, and off-chip memory access. As an alternative, Resistive Random Access Memories (RRAMs), have been proposed to store weights on chip with higher density and enabling fast analog computation with low power consumption. Conductive Bridge Random Access Memories (CBRAMs) is a subset of RRAMs, whose conductance states is defined by the existence and modulation of a conductive metal filament. Ag-Chalcogenide based Conductive Bridge RAM (CBRAM) devices have demonstrated multiple resistive states making them potential candidates for use as analog synapses in neuromorphic hardware. In this work the use of Ag-Ge30Se70 device as an analog synaptic device has been explored. Ag-Ge30Se70 CBRAM crossbar array was fabricated. The fabricated crossbar devices were subjected to different pulsing schemes and conductance linearity response was analyzed. An improved linear response of the devices from a non-linearity factor of 6.65 to 1 for potentiation and -2.25 to -0.95 for depression with non-identical pulse application is observed. The effect of improved linearity was quantified by simulating the devices in an artificial neural network. Simulations for area, latency, and power consumption of the CBRAM device in a neural accelerator was conducted. Further, the changes caused by Total Ionizing Dose (TID) in the conductance of the analog response of Ag-Ge30Se70 Conductive Bridge Random Access Memory (CBRAM)-based synapses are studied. The effect of irradiation was further analyzed by simulating the devices in an artificial neural network. Material characterization was performed to understand the change in conductance observed due to TID.
ContributorsApsangi, Priyanka (Author) / Barnaby, Hugh (Thesis advisor) / Kozicki, Michael (Committee member) / Sanchez Esqueda, Ivan (Committee member) / Marinella, Matthew (Committee member) / Arizona State University (Publisher)
Created2022
Description
This thesis presents a code generation tool to improve the programmability of systolic array processors such as the Domain Adaptive Processor (DAP) that was designed by researchers at the University of Michigan for wireless communication workloads. Unlike application-specific integrated circuits, DAP aims to achieve high performance without trading off much on programmability and reconfigurability. The structure of a typical DAP code for each Processing Element (PE) is very different from any other programming language format. As a result, writing code for DAP requires the programmer to acquire processor-specific knowledge including configuration rules, cycle accurate execution state for memory and datapath components within each PE, etc. Each code must be carefully handcrafted to meet the strict timing and resource constraints, leading to very long programming times and low productivity. In this thesis, a code generation and optimization tool is introduced to improve the programmability of DAP and make code development easier. The tool consists of a configuration code generator, optimizer, and a scheduler. An Instruction Set Architecture (ISA) has been designed specifically for DAP. The programmer writes the assembly code for each PE using the DAP ISA. The assembly code is then translated into a low-level configuration code. This configuration code undergoes several optimizations passes. Level 1 (L1) optimization handles instruction redundancy and performs loop optimizations through code movement. The Level 2 (L2) optimization performs instruction-level parallelism. Use of L1 and L2 optimization passes result in a code that has fewer instructions and requires fewer cycles. In addition, a scheduling tool has been introduced which performs final timing adjustments on the code to match the input data rate.
ContributorsVipperla, Anish (Author) / Chakrabarti, Chaitali (Thesis advisor) / Bliss, Daniel (Committee member) / Akoglu, Ali (Committee member) / Arizona State University (Publisher)
Created2022
Description
Modeling protection devices is essential for performing accurate stability studies. Modeling all the protection devices in a bulk power system is an intractable task due to the limitations of current stability software, and the difficulty in updating the setting data for thousands of protection devices. One of the critical protection schemes that is not adequately modeled in stability studies is distance relaying. Therefore, this dissertation proposes two different methods for identifying the critical distance relays for any contingency, which are required to be modeled in stability studies. The first method is an iterative analytical algorithm and the second method is an ML-based method. The performances of both the methods are evaluated on the Western Electricity Coordinating Council (WECC) system and the results show that to have an accurate assessment of system behavior, modeling the critical distance suffices, and modeling all the distance relays in not necessary. Furthermore, modeling various generator protective relays in stability studies is also crucial. However, no comprehensive framework has been developed that provides guidelines on proper representation of generator protective relays in stability studies and evaluate their impact on the dynamic response of a system. To fill this gap, this dissertation proposes a comprehensive systematic framework which enables proper representation of generator protective relays in stability studies, thereby increasing the accuracy of these studies. The framework is tested on a particular area of the WECC system and the behaviors of different generator protective relays is evaluated.Finally, this dissertation proposes a comprehensive machine-learning (ML)-based online dynamic security assessment (DSA) method that broaden the concept of online DSA by predicting loss of synchronism (LOS) in generators, and the operation of critical protective relays in a power system. The performance of the method is tested on the WECC system in the presence of different noise levels and missing phasor measurement unit (PMU) data. The results reveal that the method can provide precise and fast predictions and is robust to noise and missing PMU data. Therefore, the method can be reliably used in power systems to enhance situational awareness by providing early warnings of impending problems in the system.
ContributorsVakili, Ramin (Author) / Hedman, Mojdeh MKH (Thesis advisor) / Wu, Meng MW (Committee member) / Ayyanar, Raja RA (Committee member) / Vittal, Vijay VV (Committee member) / Arizona State University (Publisher)
Created2022
Description
The fast growth of the power system industry and the increase in the usage of computerized management systems introduces more complexities to power systems operations. Although these computerized management systems help system operators manage power systems reliably and efficiently, they introduce the threat of cyber-attacks. In this regard, this dissertation focuses on the load-redistribution (LR) attacks, which cause overflows in power systems. Previous researchers have shown the possibility of launching undetectable LR attacks against power systems, even when protection schemes exist. This fact pushes researchers to develop detection mechanisms. In this thesis, real-time detection mechanisms are developed based on the fundamental knowledge of power systems, operation research, and machine learning. First, power systems domain insight is used to identify an underlying exploitable structure for the core problem of LR attacks. Secondly, a greedy algorithm’s ability to solve the identified structure to optimality is proved, which helps operators quickly find the best attack vector and the most sensitive buses for each target transmission asset. Then, two quantitative security indices are proposed and leveraged to develop a measurement threat analysis (MTA) tool. Finally, a machine learning-based classifier is used to enhance the MTA tool’s functionality in flagging tiny LR attacks and distinguishing them from measurement/forecasting errors. On the other hand, after acknowledging that an adversarial LR attack interferes with the system, establishing a corrective action is imperative to mitigate or remove the potential consequences of the attack. This dissertation proposes two corrective actions; the first one is developed based on the worst-case attack scenario, considering the information provided by the MTA tool. After The MTA tool flags an LR attack in the system, it should determine the primary target and other affected transmission assets, using which the operator can estimate the actual loads in the post-attack stage. This estimation is essential since the corresponding security constraints in the first corrective action model are modeled based on these loads. The second one is a robust optimization that considers various load scenarios. The functionality of this robust model does not depend on the information provided by the MTA tool and is more reliable.
ContributorsKaviani, Ramin (Author) / Hedman, Kory (Thesis advisor) / Vittal, Vijay (Committee member) / Hedman, Mojdeh (Committee member) / Wu, Meng (Committee member) / Arizona State University (Publisher)
Created2022
Description
Gallium Nitride (GaN) is uniquely suited for Radio Frequency (RF) and power electronic applications due to its intrinsically high saturation velocity and high mobility compared to Silicon and Silicon Carbide (SiC). High Electron Mobility Transistors (HEMTs) have remained the primary topology for GaN transistors in RF applications. However, GaN HEMTs suffer from a variety of issues such as current crowding, lack of enhancement mode (E-Mode) operation and non-linearity. These drawbacks slow the widespread adoption of GaN devices for ultra-low voltage (ULV) applications such as voltage regulators, automotive and computing applications. E-mode operation is especially desired in low-voltage high frequency switching applications. In this context, Fin Field Effect Transistors (FinFETs) offer an alternative topology for ULV applications as opposed to conventional HEMTs. Recent advances in material processing, high aspect ratio epitaxial growth and etching methods has led to an increased interest in 3D nanostructures such as Nano-FinFETs and Nanowire FETs. A typical 3D nano-FinFET is the AlGaN/GaN Metal Insulator Semiconductor (MIS) FET wherein a layer of Al2O3 surrounds the AlGaN/GaN fin. The presence of the side gates leads to additional lateral confinement of the 2D Electron Gas (2DEG). Theoretical calculations of transport properties in confined systems such as AlGaN/GaN Finfets are scarce compared to those of their planar HEMT counterparts.
A novel simulator is presented in this dissertation, which employs self-consistent solution of the coupled 1D Boltzmann – 2D Schrödinger – 3D Poisson problem, to yield the channel electrostatics and the low electric field transport characteristics of AlGaN/GaN MIS FinFETs. The low field electron mobility is determined by solving the Boltzmann transport equation in the Quasi-1D region using 1D Ensemble Monte Carlo method. Three electron-phonon scattering mechanisms (acoustic, piezoelectric and polar optical phonon scattering) and interface roughness scattering at the AlGaN/GaN interface are considered in this theoretical model. Simulated low-field electron mobility and its temperature dependence are in agreement with experimental data reported in the literature.
A quasi-1D version of alloy clustering model is derived and implemented and the limiting effect of alloy clustering on the low-field electron mobility is investigated for the first time for MIS FinFET device structures.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Povolotskyi, Michael (Committee member) / Esqueda, Ivan Sanchez (Committee member) / Arizona State University (Publisher)
Created2022