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Description
This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
1) A transformer-based power combiner architecture for out-phasing transmitters
2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)
3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters
This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.
The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.
Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.
ContributorsMoallemi, Soroush (Author) / Kitchen, Jennifer (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2019
Description
This dissertation details the development of an open source, frequency domain multiplexed (FDM) readout for large-format arrays of superconducting lumped-element kinetic inductance detectors (LEKIDs). The system architecture is designed to meet the requirements of current and next generation balloon-borne and ground-based submillimeter (sub-mm), far-infrared (FIR) and millimeter-wave (mm-wave) astronomical cameras, whose science goals will soon drive the pixel counts of sub-mm detector arrays from the kilopixel to the megapixel regime. The in-flight performance of the readout system was verified during the summer, 2018 flight of ASI's OLIMPO balloon-borne telescope, from Svalbard, Norway. This was the first flight for both LEKID detectors and their associated readout electronics. In winter 2019/2020, the system will fly on NASA's long-duration Balloon Borne Large Aperture Submillimeter Telescope (BLAST-TNG), a sub-mm polarimeter which will map the polarized thermal emission from cosmic dust at 250, 350 and 500 microns (spatial resolution of 30", 41" and 59"). It is also a core system in several upcoming ground based mm-wave instruments which will soon observe at the 50 m Large Millimeter Telescope (e.g., TolTEC, SuperSpec, MUSCAT), at Sierra Negra, Mexico.
The design and verification of the FPGA firmware, software and electronics which make up the system are described in detail. Primary system requirements are derived from the science objectives of BLAST-TNG, and discussed in the context of relevant size, weight, power and cost (SWaP-C) considerations for balloon platforms. The system was used to characterize the instrumental performance of the BLAST-TNG receiver and detector arrays in the lead-up to the 2019/2020 flight attempt from McMurdo Station, Antarctica. The results of this characterization are interpreted by applying a parametric software model of a LEKID detector to the measured data in order to estimate important system parameters, including the optical efficiency, optical passbands and sensitivity.
The role that magnetic fields (B-fields) play in shaping structures on various scales in the interstellar medium is one of the central areas of research which is carried out by sub-mm/FIR observatories. The Davis-Chandrasekhar-Fermi Method (DCFM) is applied to a BLASTPol 2012 map (smoothed to 5') of the inner ~1.25 deg2 of the Carina Nebula Complex (CNC, NGC 3372) in order to estimate the strength of the B-field in the plane-of-the-sky (B-pos). The resulting map contains estimates of B-pos along several thousand sightlines through the CNC. This data analysis pipeline will be used to process maps of the CNC and other science targets which will be produced during the upcoming BLAST-TNG flight. A target selection survey of five nearby external galaxies which will be mapped during the flight is also presented.
The design and verification of the FPGA firmware, software and electronics which make up the system are described in detail. Primary system requirements are derived from the science objectives of BLAST-TNG, and discussed in the context of relevant size, weight, power and cost (SWaP-C) considerations for balloon platforms. The system was used to characterize the instrumental performance of the BLAST-TNG receiver and detector arrays in the lead-up to the 2019/2020 flight attempt from McMurdo Station, Antarctica. The results of this characterization are interpreted by applying a parametric software model of a LEKID detector to the measured data in order to estimate important system parameters, including the optical efficiency, optical passbands and sensitivity.
The role that magnetic fields (B-fields) play in shaping structures on various scales in the interstellar medium is one of the central areas of research which is carried out by sub-mm/FIR observatories. The Davis-Chandrasekhar-Fermi Method (DCFM) is applied to a BLASTPol 2012 map (smoothed to 5') of the inner ~1.25 deg2 of the Carina Nebula Complex (CNC, NGC 3372) in order to estimate the strength of the B-field in the plane-of-the-sky (B-pos). The resulting map contains estimates of B-pos along several thousand sightlines through the CNC. This data analysis pipeline will be used to process maps of the CNC and other science targets which will be produced during the upcoming BLAST-TNG flight. A target selection survey of five nearby external galaxies which will be mapped during the flight is also presented.
ContributorsGordon, Samuel, Ph.D (Author) / Mauskopf, Philip (Thesis advisor) / Groppi, Christopher (Committee member) / Scowen, Paul (Committee member) / Bowman, Judd (Committee member) / Jacobs, Daniel (Committee member) / Arizona State University (Publisher)
Created2019
Description
The objective of this work is to design a novel method for imaging targets and scenes which are not directly visible to the observer. The unique scattering properties of terahertz (THz) waves can turn most building surfaces into mirrors, thus allowing someone to see around corners and various occlusions. In the visible regime, most surfaces are very rough compared to the wavelength. As a result, the spatial coherency of reflected signals is lost, and the geometry of the objects where the light bounced on cannot be retrieved. Interestingly, the roughness of most surfaces is comparable to the wavelengths at lower frequencies (100 GHz – 10 THz) without significantly disturbing the wavefront of the scattered signals, behaving approximately as mirrors. Additionally, this electrically small roughness is beneficial because it can be used by the THz imaging system to locate the pose (location and orientation) of the mirror surfaces, thus enabling the reconstruction of both line-of-sight (LoS) and non-line-of-sight (NLoS) objects.
Back-propagation imaging methods are modified to reconstruct the image of the 2-D scenario (range, cross-range). The reflected signal from the target is collected using a SAR (Synthetic Aperture Radar) set-up in a lab environment. This imaging technique is verified using both full-wave 3-D numerical analysis models and lab experiments.
The novel imaging approach of non-line-of-sight-imaging could enable novel applications in rescue and surveillance missions, highly accurate localization methods, and improve channel estimation in mmWave and sub-mmWave wireless communication systems.
Back-propagation imaging methods are modified to reconstruct the image of the 2-D scenario (range, cross-range). The reflected signal from the target is collected using a SAR (Synthetic Aperture Radar) set-up in a lab environment. This imaging technique is verified using both full-wave 3-D numerical analysis models and lab experiments.
The novel imaging approach of non-line-of-sight-imaging could enable novel applications in rescue and surveillance missions, highly accurate localization methods, and improve channel estimation in mmWave and sub-mmWave wireless communication systems.
ContributorsDoddalla, Sai Kiran kiran (Author) / Trichopoulos, George (Thesis advisor) / Alkhateeb, Ahmed (Committee member) / Zeinolabedinzadeh, Saeed (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2019
Description
This dissertation studies load balancing algorithms for many-server systems (with N servers) and focuses on the steady-state performance of load balancing algorithms in the heavy traffic regime. The framework of Stein’s method and (iterative) state-space collapse (SSC) are used to analyze three load balancing systems: 1) load balancing in the Sub-Halfin-Whitt regime with exponential service time; 2) load balancing in the Beyond-Halfin-Whitt regime with exponential service time; 3) load balancing in the Sub-Halfin-Whitt regime with Coxian-2 service time.
When in the Sub-Halfin-Whitt regime, the sufficient conditions are established such that any load balancing algorithm that satisfies the conditions have both asymptotic zero waiting time and zero waiting probability. Furthermore, the number of servers with more than one jobs is o(1), in other words, the system collapses to a one-dimensional space. The result is proven using Stein’s method and state space collapse (SSC), which are powerful mathematical tools for steady-state analysis of load balancing algorithms. The second system is in even “heavier” traffic regime, and an iterative refined procedure is proposed to obtain the steady-state metrics. Again, asymptotic zero delay and waiting are established for a set of load balancing algorithms. Different from the first system, the system collapses to a two-dimensional state-space instead of one-dimensional state-space. The third system is more challenging because of “non-monotonicity” with Coxian-2 service time, and an iterative state space collapse is proposed to tackle the “non-monotonicity” challenge. For these three systems, a set of load balancing algorithms is established, respectively, under which the probability that an incoming job is routed to an idle server is one asymptotically at steady-state. The set of load balancing algorithms includes join-the-shortest-queue (JSQ), idle-one-first(I1F), join-the-idle-queue (JIQ), and power-of-d-choices (Pod) with a carefully-chosen d.
When in the Sub-Halfin-Whitt regime, the sufficient conditions are established such that any load balancing algorithm that satisfies the conditions have both asymptotic zero waiting time and zero waiting probability. Furthermore, the number of servers with more than one jobs is o(1), in other words, the system collapses to a one-dimensional space. The result is proven using Stein’s method and state space collapse (SSC), which are powerful mathematical tools for steady-state analysis of load balancing algorithms. The second system is in even “heavier” traffic regime, and an iterative refined procedure is proposed to obtain the steady-state metrics. Again, asymptotic zero delay and waiting are established for a set of load balancing algorithms. Different from the first system, the system collapses to a two-dimensional state-space instead of one-dimensional state-space. The third system is more challenging because of “non-monotonicity” with Coxian-2 service time, and an iterative state space collapse is proposed to tackle the “non-monotonicity” challenge. For these three systems, a set of load balancing algorithms is established, respectively, under which the probability that an incoming job is routed to an idle server is one asymptotically at steady-state. The set of load balancing algorithms includes join-the-shortest-queue (JSQ), idle-one-first(I1F), join-the-idle-queue (JIQ), and power-of-d-choices (Pod) with a carefully-chosen d.
ContributorsLiu, Xin (Author) / Ying, Lei (Thesis advisor) / Maguluri, Siva Theja (Committee member) / Wang, Weina (Committee member) / Zhang, Junshan (Committee member) / Arizona State University (Publisher)
Created2019
Description
An analysis is presented of a network of distributed receivers encumbered by strong in-band interference. The structure of information present across such receivers and how they might collaborate to recover a signal of interest is studied. Unstructured (random coding) and structured (lattice coding) strategies are studied towards this purpose for a certain adaptable system model. Asymptotic performances of these strategies and algorithms to compute them are developed. A jointly-compressed lattice code with proper configuration performs best of all strategies investigated.
ContributorsChapman, Christian Douglas (Author) / Bliss, Daniel W (Thesis advisor) / Richmond, Christ D (Committee member) / Kosut, Oliver (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Arizona State University (Publisher)
Created2019
Description
As the world becomes more electronic, power electronics designers have continuously designed more efficient converters. However, with the rising number of nonlinear loads (i.e. electronics) attached to the grid, power quality concerns, and emerging legislation, converters that intake alternating current (AC) and output direct current (DC) known as rectifiers are increasingly implementing power factor correction (PFC) by controlling the input current. For a properly designed PFC-stage inductor, the major design goals include exceeding minimum inductance, remaining below the saturation flux density, high power density, and high efficiency. In meeting these goals, loss calculation is critical in evaluating designs. This input current from PFC circuitry leads to a DC bias through the filter inductor that makes accurate core loss estimation exceedingly difficult as most modern loss estimation techniques neglect the effects of a DC bias. This thesis explores prior loss estimation and design methods, investigates finite element analysis (FEA) design tools, and builds a magnetics test bed setup to empirically determine a magnetic core’s loss under any electrical excitation. In the end, the magnetics test bed hardware results are compared and future work needed to improve the test bed is outlined.
ContributorsMeyers, Tobin (Author) / Ayyanar, Raja (Thesis advisor) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2019
Description
Modern Communication systems are progressively moving towards all-digital transmitters (ADTs) due to their high efficiency and potentially large frequency range. While significant work has been done on individual blocks within the ADT, there are few to no full systems designs at this point in time. The goal of this work is to provide a set of multiple novel block architectures which will allow for greater cohesion between the various ADT blocks. Furthermore, the design of these architectures are expected to focus on the practicalities of system design, such as regulatory compliance, which here to date has largely been neglected by the academic community. Amongst these techniques are a novel upconverted phase modulation, polyphase harmonic cancellation, and process voltage and temperature (PVT) invariant Delta Sigma phase interpolation. It will be shown in this work that the implementation of the aforementioned architectures allows ADTs to be designed with state of the art size, power, and accuracy levels, all while maintaining PVT insensitivity. Due to the significant performance enhancement over previously published works, this work presents the first feasible ADT architecture suitable for widespread commercial deployment.
ContributorsGrout, Kevin Samuel (Author) / Kitchen, Jennifer N (Thesis advisor) / Khalil, Waleed (Committee member) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Garrity, Douglas (Committee member) / Arizona State University (Publisher)
Created2019
Description
This dissertation covers three primary topics and relates them in context. High frequency transformer design, microgrid modeling and control, and converter design as it pertains to the other topics are each investigated, establishing a summary of the state-of-the-art at the intersection of the three as a baseline. The culminating work produced by the confluence of these topics is a novel modular solid-state transformer (SST) design, featuring an array of dual active bridge (DAB) converters, each of which contains an optimized high-frequency transformer, and an array of grid-forming inverters (GFI) suitable for centralized control in a microgrid environment. While no hardware was produced for this design, detailed modeling and simulation has been completed, and results are contextualized by rigorous analysis and comparison with results from published literature. The main contributions to each topic are best presented by topic area. For transformers, contributions include collation and presentation of the best-known methods of minimum loss high-frequency transformer design and analysis, descriptions of the implementation of these methods into a unified design script as well as access to an example of such a script, and the derivation and presentation of novel tools for analysis of multi-winding and multi-frequency transformers. For microgrid modeling and control, contributions include the modeling and simulation validation of the GFI and SST designs via state space modeling in a multi-scale simulation framework, as well as demonstration of stable and effective participation of these models in a centralized control scheme under phase imbalance. For converters, the SST design, analysis, and simulation are the primary contributions, though several novel derivations and analysis tools are also presented for the asymmetric half bridge and DAB.
ContributorsMongrain, Robert Scott (Author) / Ayyanar, Raja (Thesis advisor) / Pan, George (Committee member) / Qin, Jiangchao (Committee member) / Lei, Qin (Committee member) / Arizona State University (Publisher)
Created2019
Description
Readout Integrated Circuits(ROICs) are important components of infrared(IR) imag
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ing systems. Performance of ROICs affect the quality of images obtained from IR
imaging systems. Contemporary infrared imaging applications demand ROICs that
can support large dynamic range, high frame rate, high output data rate, at low
cost, size and power. Some of these applications are military surveillance, remote
sensing in space and earth science missions and medical diagnosis. This work focuses
on developing a ROIC unit cell prototype for National Aeronautics and Space Ad
ministration(NASA), Jet Propulsion Laboratory’s(JPL’s) space applications. These
space applications also demand high sensitivity, longer integration times(large well
capacity), wide operating temperature range, wide input current range and immunity
to radiation events such as Single Event Latchup(SEL).
This work proposes a digital ROIC(DROIC) unit cell prototype of 30ux30u size,
to be used mainly with NASA JPL’s High Operating Temperature Barrier Infrared
Detectors(HOT BIRDs). Current state of the art DROICs achieve a dynamic range
of 16 bits using advanced 65-90nm CMOS processes which adds a lot of cost overhead.
The DROIC pixel proposed in this work uses a low cost 180nm CMOS process and
supports a dynamic range of 20 bits operating at a low frame rate of 100 frames per
second(fps), and a dynamic range of 12 bits operating at a high frame rate of 5kfps.
The total electron well capacity of this DROIC pixel is 1.27 billion electrons, enabling
integration times as long as 10ms, to achieve better dynamic range. The DROIC unit
cell uses an in-pixel 12-bit coarse ADC and an external 8-bit DAC based fine ADC.
The proposed DROIC uses layout techniques that make it immune to radiation up to
300krad(Si) of total ionizing dose(TID) and single event latch-up(SEL). It also has a
wide input current range from 10pA to 1uA and supports detectors operating from
Short-wave infrared (SWIR) to longwave infrared (LWIR) regions.
ContributorsPraveen, Subramanya Chilukuri (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kitchen, Jennifer (Committee member) / Long, Yu (Committee member) / Arizona State University (Publisher)
Created2019
Description
Presented is a design approach and test of a novel compact waveguide that demonstrated the outer dimensions of a rectangular waveguide through the introduction of parallel raised strips, or flanges, which run the length of the rectangular waveguide along the direction of wave propagation. A 10GHz waveguide was created with outer dimensions of a=9.0mm and b=3.6mm compared to a WR-90 rectangular waveguide with outer dimensions of a=22.86mm and b=10.16mm which the area is over 7 times the area. The first operating bandwidth for a hollow waveguide of dimensions a=9.0mm and b=3.6mm starts at 16.6GHz a 40% reduction in cutoff frequency.
The prototyped and tested compact waveguide demonstrated an operating close to the predicted 2GHz with predicted vs measured injection loss generally within 0.25dB and an overall measured injection loss of approximately 4.67dB/m within the operating bandwidth.
The prototyped and tested compact waveguide demonstrated an operating close to the predicted 2GHz with predicted vs measured injection loss generally within 0.25dB and an overall measured injection loss of approximately 4.67dB/m within the operating bandwidth.
ContributorsJones, Jimmy, Ph.D (Author) / Pan, George (Thesis advisor) / Palais, Joseph (Committee member) / Aberle, James T., 1961- (Committee member) / Young, William (Committee member) / Arizona State University (Publisher)
Created2019