Matching Items (68)
Filtering by
- All Subjects: Electrical Engineering
- Creators: Vasileska, Dragica
Description
As the single-junction silicon solar cell is approaching its theoretical efficiency limits, the loss from shading and resistance is gaining increasing attention. The metal grid pattern may cause an efficiency loss up to 1–3%abs (absolute percentage) depending on the grid’s materials and structure.Many attempts have been proposed to reduce the loss caused by the contacts and module. Among them, the monolithic solar cell, which is a solar cell with multiple string cells on the same wafer and connected in a series, presents advantages of low output current, busbar-free contact, minimized interconnection space, and ohmic loss reduction. However, this structure also introduces a lateral forward bias current through the base region, which severely degrades the cell’s performance. In addition, this interconnection in the base region has partially shunted certain solar cells in the monolithic cell, which created a mismatch between string cells.
For the last few decades, researchers have used different methods such as etching trenches or enlarging the distance between the neighboring string cells to solve this problem. However, these methods were both ineffective and defective.
In this work, a novel method of suppressing the lateral forward bias current is proposed. By adding a very high surface recombination to the mid-region between the string cells, the carrier density in the mid-region can be decreased close to the doping density. Thus, the resistivity in the mid-region can be increased tenfold or more. As a result, the lateral forward bias current is greatly reduced.
Other methods to reduce lateral forward bias current include optimizing the width of the mid-region, shading the mid-region, reducing the base doping and base thickness which can be used to reduce the mismatch as well.
Another method has been proposed to calculate the minimum efficiency loss of a monolithic cell compared to the baseline solar cell. As a result, the monolithic cell could potentially gain more advantages over the baseline solar cells with a thinner and low-doped wafer.
A monolithic solar cell with innovative designs is presented in this work which shows an efficiency that is potentially higher than that of normal solar cells.
ContributorsXue, Shujian (Author) / Bowden, Studart (Thesis advisor) / Goodnick, Stephen (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2022
Description
CdTe/MgCdTe double heterostructures (DHs) integrated with a heavily-doped a-Si:H layer as the hole contact was demonstrated a record open-circuit voltage (VOC) of 1.11 V and an active-area efficiency of 20% in 2016. Despite this significant progress, some of the underlying device physics has not been fully understood. The first part of this dissertation reports a systematic study of the CdTe/MgCdTe DH devices. The CdTe/MgCdTe DHs are grown on InSb(001) substrates. The vertical transport mechanisms across the CdTe and InSb heterovalent interface are investigated with N-CdTe/n-InSb and N-CdTe/p-InSb heterostructures. A transport model including tunneling through CdTe barrier and InSb interband transition is developed to explain the different temperature dependent current-voltage characteristics of these two heterostructures.
Different p-type layers are integrated with the CdTe/MgCdTe DHs to form solar cells with different VOC values and efficiencies. The low VOC of devices with ZnTe:Cu and ZnTe:As hole contacts is attributed to the low built-in voltage and reduced minority carrier lifetime in the CdTe absorber, respectively. The critical requirements for reaching high VOC values are analyzed.
A novel epitaxial lift-off technology for monocrystalline CdTe is developed using a water-soluble and nearly lattice-matched MgTe sacrificial layer grown on InSb substrate. The freestanding CdTe/MgCdTe DH thin films obtained from the lift-off process show improved optical performance due to enhanced light extraction efficiency and photo-recycling effect. This technology enables the possible development of monocrystalline CdTe thin-film solar cells and 1.7/1.1-eV MgCdTe/Si or MgCdTe/Cu(InGa)Se2 tandem solar cells. The monocrystalline CdTe thin-film solar cells and 1.7-eV MgCdTe DH solar cells have been demonstrated with a power conversion efficiency of 9.8% and an active-area efficiency as high as 15.2%, respectively. Additionally, a study of the radiation effects on CdTe DHs under 68-MeV proton irradiation is performed and showed their superior radiation tolerance. All these findings indicate that the monocrystalline CdTe thin-film solar cells are reasonably expected to have low weight, high-efficiency and high power density, ideal for space applications.
ContributorsDing, Jia (Author) / Zhang, Yong-Hang (Thesis advisor) / Vasileska, Dragica (Committee member) / Johnson, Shane (Committee member) / Holman, Zachary (Committee member) / Arizona State University (Publisher)
Created2021
Description
The goal of this research work is to develop an understanding as well as modelling thermal effects in Si based nano-scale devices using a multiscale simulator tool. This tool has been developed within the research group at Arizona State University led by Professor Dr. Dragica Vasileska. Another research group, headed by Professor Dr. Thornton, also at Arizona State University, provided support with software tools, by not only laying out the physical experimental device, but also provided experimental data to verify the correctness and accuracy of the developed simulation tool. The tool consists of three separate but conjoined modules at different scales of representation. 1) A particle based, ensemble Monte Carlo (MC) simulation tool, which, in the long-time (electronic motion) limit, solves the Boltzmann transport equation (BTE) for electrons, coupled with an iterative solution to a two-dimensional (2D) Poisson’s equation, at the base device level. 2) Another device level thermal modeling tool which solves the energy balance equations accounting for carrier-phonon and phonon-phonon interactions and is integrated with the MC tool. 3) Lastly, a commercial technology computer aided design (TCAD) software, Silvaco is employed to incorporate the results from the above two tools to a circuit level, common-source dual-transistor circuit, where one of the devices acts a heater and the other as a sensor, to study the impacts of thermal heating. The results from this tool are fed back to the previous device level tools to iterate on, until a stable, unified electro-thermal equilibrium/result is obtained. This coupled electro-thermal approach was originally developed for an individual n-channel MOSFET (NMOS) device by Prof. Katerina Raleva and was extended to allow for multiple devices in tandem, thereby providing a platform for better and more accurate modeling of device behavior, analyzing circuit performance, and understanding thermal effects. Simulating this dual device circuit and analyzing the extracted voltage transfer and output characteristics verifies the efficacy of this methodology as the results obtained from this multi-scale, electro-thermal simulator tool, are found to be in good general agreement with the experimental data.
ContributorsQazi, Suleman Sami (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen M (Committee member) / Thornton, Trevor J (Committee member) / Ferry, David K (Committee member) / Arizona State University (Publisher)
Created2021
Description
Gallium Nitride (GaN) is uniquely suited for Radio Frequency (RF) and power electronic applications due to its intrinsically high saturation velocity and high mobility compared to Silicon and Silicon Carbide (SiC). High Electron Mobility Transistors (HEMTs) have remained the primary topology for GaN transistors in RF applications. However, GaN HEMTs suffer from a variety of issues such as current crowding, lack of enhancement mode (E-Mode) operation and non-linearity. These drawbacks slow the widespread adoption of GaN devices for ultra-low voltage (ULV) applications such as voltage regulators, automotive and computing applications. E-mode operation is especially desired in low-voltage high frequency switching applications. In this context, Fin Field Effect Transistors (FinFETs) offer an alternative topology for ULV applications as opposed to conventional HEMTs. Recent advances in material processing, high aspect ratio epitaxial growth and etching methods has led to an increased interest in 3D nanostructures such as Nano-FinFETs and Nanowire FETs. A typical 3D nano-FinFET is the AlGaN/GaN Metal Insulator Semiconductor (MIS) FET wherein a layer of Al2O3 surrounds the AlGaN/GaN fin. The presence of the side gates leads to additional lateral confinement of the 2D Electron Gas (2DEG). Theoretical calculations of transport properties in confined systems such as AlGaN/GaN Finfets are scarce compared to those of their planar HEMT counterparts.
A novel simulator is presented in this dissertation, which employs self-consistent solution of the coupled 1D Boltzmann – 2D Schrödinger – 3D Poisson problem, to yield the channel electrostatics and the low electric field transport characteristics of AlGaN/GaN MIS FinFETs. The low field electron mobility is determined by solving the Boltzmann transport equation in the Quasi-1D region using 1D Ensemble Monte Carlo method. Three electron-phonon scattering mechanisms (acoustic, piezoelectric and polar optical phonon scattering) and interface roughness scattering at the AlGaN/GaN interface are considered in this theoretical model. Simulated low-field electron mobility and its temperature dependence are in agreement with experimental data reported in the literature.
A quasi-1D version of alloy clustering model is derived and implemented and the limiting effect of alloy clustering on the low-field electron mobility is investigated for the first time for MIS FinFET device structures.
ContributorsKumar, Viswanathan Naveen (Author) / Vasileska, Dragica (Thesis advisor) / Goodnick, Stephen (Committee member) / Nemanich, Robert (Committee member) / Povolotskyi, Michael (Committee member) / Esqueda, Ivan Sanchez (Committee member) / Arizona State University (Publisher)
Created2022
Description
Improving solar cell efficiency is an enormously powerful driver of the cost reduction of solar power. While the silicon solar cell efficiency approaches theoretical limits, many thin-film solar cell technologies fall behind. In particular, cadmium telluride (CdTe) solar cells have only reached a maximum efficiency of 22.1%. One of the challenges associated with the development of CdTe solar cells is due its high electron affinity and the difficulty of achieving heavy p-type doping. This challenge results in the formation of a Schottky barrier at the hole contact, which reduces solar cell efficiency, primarily through the reduction of open circuit voltage (Voc) and fill factor (FF). The Schottky barrier makes the characterization of the actual solar cell p-n junction through current voltage (I-V), capacitance voltage (C-V), and thermal admittance spectroscopy (TAS) more difficult and not straightforward. However, interpreted through accurate physical models and under the correct experimental conditions, these techniques can then also be used to extract the impact of the contact on device performance, chiefly through analysis of the barrier height. Additionally, characterization of the open circuit voltage as a function of the illumination intensity (Suns-Voc) and the open circuit voltage as a function of temperature [Voc(T)] offer insight into the potential impact of the contact barrier. A comprehensive review of characterization of the barrier through the above techniques is given, primarily through a two-diode model. Further, a discussion of the utility of electrochemical capacitance-voltage (ECV) profiling to recover carrier concentrations in device regions otherwise difficult to access through traditional C-V measurements is provided along with modeling to support this conclusion. A discussion of and justification for the experimental extraction of barrier height from TAS measurements are also provided. Experimentally measured Voc(T), C-V, and Suns-Voc characteristics are presented and compared for a CdTe and a gallium arsenide (GaAs) solar cell. Experimental results indicate that the contact barriers and other possible non-idealities strongly affect the performance of the CdTe solar cell. Modeling results demonstrate the use of ECV to characterize solar cell absorbers can offer information unavailable via conventional C-V measurements.
ContributorsRosenblatt, Nathan (Author) / Zhang, Yong-Hang (Thesis advisor) / King, Richard R (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2021
Description
The research of alternative materials and new device architectures to exceed the limits of conventional silicon-based devices has been sparked by the persistent pursuit of semiconductor technology scaling. The development of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2), well-known member of the transition metal dichalcogenide (TMD) family, has made great strides towards ultrascaled two-dimensional (2D) field-effect-transistors (FETs). The scaling issues facing silicon-based complementary metal-oxide-semiconductor (CMOS) technologies can be solved by 2D FETs, which show extraordinary potential.This dissertation provides a comprehensive experimental analysis relating to improvements in p-type metal-oxide-semiconductor (PMOS) FETs with few-layer WSe2 and high-κ metal gate (HKMG) stacks. Compared to this works improved methods, standard metallization (more damaging to underlying channel) results in significant Fermi-level pinning, although Schottky barrier heights remain small (< 100 meV) when using high work function metals. Temperature-dependent analysis reveals a dominant contribution to contact resistance from the damaged channel access region. Thus, through less damaging metallization methods combined with strongly scaled HKMG stacks significant improvements were achieved in contact resistance and PMOS FET overall performance. A clean contact/channel interface was achieved through high-vacuum evaporation and temperature-controlled stepped deposition. Theoretical analysis using a Landauer transport adapted to WSe2 Schottky barrier FETs (SB-FETs) elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance towards the ultimate CMOS scaling limit.
Next, this dissertation discusses how device electrical characteristics are affected by scaling of equivalent oxide thickness (EOT) and by adopting double-gate FET architectures, as well as how this might support CMOS scaling. An improved gate control over the channel is made possible by scaling EOT, improving on-off current ratios, carrier mobility, and subthreshold swing. This study also elucidates the impact of EOT scaling on FET gate hysteresis attributed to charge-trapping effects in high-κ-dielectrics prepared by atomic layer deposition (ALD). These developments in 2D FETs offer a compelling alternative to conventional silicon-based devices and a path for continued transistor scaling. This research contributes to ongoing efforts in 2D materials for future semiconductor technologies. Finally, this work introduces devices based on emerging Janus TMDs and bismuth oxyselenide (Bi2O2Se) layered semiconductors.
ContributorsPatoary, Md Naim Hossain (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Tongay, Sefaattin (Committee member) / Vasileska, Dragica (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2023
Description
In the last few decades, extensive research efforts have been focused on scaling down silicon-based complementary metal-oxide semiconductor (CMOS) technology to enable the continuation of Moore’s law. State-of-art CMOS includes fully depleted silicon-on-insulator (FDSOI) field-effect-transistors (FETs) with ultra-thin silicon channels (6 nm), as well as other three-dimensional (3D) device architectures like Fin-FETs, nanosheet FETs, etc. Significant research efforts have characterized these technologies towards various applications, and at different conditions including a wide range of temperatures from room temperature (300 K) down to cryogenic temperatures. Theoretical efforts have studied ultrascaled devices using Landauer theory to further understand their transport properties and predict their performance in the quasi-ballistic regime.Further scaling of CMOS devices requires the introduction of new semiconducting channel materials, as now established by the research community. Here, two-dimensional (2D) semiconductors have emerged as a promising candidate to replace silicon for next-generation ultrascaled CMOS devices. These emerging 2D semiconductors also have applications beyond CMOS, for example in novel memory, neuromorphic, and spintronic devices. Graphene is a promising candidate for spintronic devices due to its outstanding spin transport properties as evidenced by numerous studies in non-local lateral spin valve (LSV) geometries. The essential components of graphene-based LSV, such as graphene FETs, metal-graphene contacts, and tunneling barriers, were individually investigated as part of this doctoral dissertation.
In this work, several contributions were made to these CMOS and beyond CMOS technologies. This includes comprehensive characterization and modeling of FDSOI nanoscale FETs from room temperature down to cryogenic temperatures. Using Landauer theory for nanoscale transistors, FDSOI devices were analyzed and modeled under quasi-ballistic operation. This was extended towards a virtual-source modeling approach that accounts for temperature-dependent quasi-ballistic transport and back-gate biasing effects. Additionally, graphene devices with ultrathin high-k gate dielectrics were investigated towards FETs, non-volatile memory, and spintronic devices. New contributions were made relating to charge trapping effects and their impact on graphene device electrostatics (Dirac voltage shifts) and transport properties (impact on mobility and conductivity). This work also studied contact resistance and tunneling effects using transfer length method (TLM) graphene FET structures and magnetic tunneling junction (MTJ) towards graphene-based LSV.
ContributorsZhou, Guantong (Author) / Sanchez Esqueda, Ivan (Thesis advisor) / Vasileska, Dragica (Committee member) / Tongay, Sefaattin (Committee member) / Thornton, Trevor (Committee member) / Arizona State University (Publisher)
Created2023
Description
One of the challenges in future semiconductor device design is excessive rise of power dissipation and device temperatures. With the introduction of new geometrically confined device structures like SOI, FinFET, nanowires and continuous incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. This work examines the degradation in the ON-current due to self-heating effects in 10 nm channel length silicon nanowire transistors. As part of this dissertation, a 3D electrothermal device simulator is developed that self-consistently solves electron Boltzmann transport equation with 3D energy balance equations for both the acoustic and the optical phonons. This device simulator predicts temperature variations and other physical and electrical parameters across the device for different bias and boundary conditions. The simulation results show insignificant current degradation for nanowire self-heating because of pronounced velocity overshoot effect. In addition, this work explores the role of various placement of the source and drain contacts on the magnitude of self-heating effect in nanowire transistors. This work also investigates the simultaneous influence of self-heating and random charge effects on the magnitude of the ON current for both positively and negatively charged single charges. This research suggests that the self-heating effects affect the ON-current in two ways: (1) by lowering the barrier at the source end of the channel, thus allowing more carriers to go through, and (2) via the screening effect of the Coulomb potential. To examine the effect of temperature dependent thermal conductivity of thin silicon films in nanowire transistors, Selberherr's thermal conductivity model is used in the device simulator. The simulations results show larger current degradation because of self-heating due to decreased thermal conductivity . Crystallographic direction dependent thermal conductivity is also included in the device simulations. Larger degradation is observed in the current along the [100] direction when compared to the [110] direction which is in agreement with the values for the thermal conductivity tensor provided by Zlatan Aksamija.
ContributorsHossain, Arif (Author) / Vasileska, Dragica (Thesis advisor) / Ahmed, Shaikh (Committee member) / Bakkaloglu, Bertan (Committee member) / Goodnick, Stephen (Committee member) / Arizona State University (Publisher)
Created2011
Description
Radiation-induced gain degradation in bipolar devices is considered to be the primary threat to linear bipolar circuits operating in the space environment. The damage is primarily caused by charged particles trapped in the Earth's magnetosphere, the solar wind, and cosmic rays. This constant radiation exposure leads to early end-of-life expectancies for many electronic parts. Exposure to ionizing radiation increases the density of oxide and interfacial defects in bipolar oxides leading to an increase in base current in bipolar junction transistors. Radiation-induced excess base current is the primary cause of current gain degradation. Analysis of base current response can enable the measurement of defects generated by radiation exposure. In addition to radiation, the space environment is also characterized by extreme temperature fluctuations. Temperature, like radiation, also has a very strong impact on base current. Thus, a technique for separating the effects of radiation from thermal effects is necessary in order to accurately measure radiation-induced damage in space. This thesis focuses on the extraction of radiation damage in lateral PNP bipolar junction transistors and the space environment. It also describes the measurement techniques used and provides a quantitative analysis methodology for separating radiation and thermal effects on the bipolar base current.
ContributorsCampola, Michael J (Author) / Barnaby, Hugh J (Thesis advisor) / Holbert, Keith E. (Committee member) / Vasileska, Dragica (Committee member) / Arizona State University (Publisher)
Created2011
Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011