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- All Subjects: engineering
- Creators: Tamizhmani, Govindasamy
- Creators: Bakkaloglu, Bertan
Description
Photovoltaic (PV) systems are one of the next generation's renewable energy sources for our world energy demand. PV modules are highly reliable. However, in polluted environments, over time, they will collect grime and dust. There are also limited field data studies about soiling losses on PV modules. The study showed how important it is to investigate the effect of tilt angle on soiling. The study includes two sets of mini-modules. Each set has 9 PV modules tilted at 0, 5, 10, 15, 20, 23, 30, 33 and 40°. The first set called "Cleaned" was cleaned every other day. The second set called "Soiled" was never cleaned after the first day. The short circuit current, a measure of irradiance, and module temperature was monitored and recorded every two minutes over three months (January-March 2011). The data were analyzed to investigate the effect of tilt angle on daily and monthly soiling, and hence transmitted solar insolation and energy production by PV modules. The study shows that during the period of January through March 2011 there was an average loss due to soiling of approximately 2.02% for 0° tilt angle. Modules at tilt anlges 23° and 33° also have some insolation losses but do not come close to the module at 0° tilt angle. Tilt anlge 23° has approximately 1.05% monthly insolation loss, and 33° tilt angle has an insolation loss of approximately 0.96%. The soiling effect is present at any tilt angle, but the magnitude is evident: the flatter the solar module is placed the more energy it will lose.
ContributorsCano Valero, José (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Madakannan, Arunachalanadar (Committee member) / Macia, Narciso (Committee member) / Arizona State University (Publisher)
Created2011
Description
Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW.
ContributorsLee, Junghan (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Song, Hongjiang (Committee member) / Arizona State University (Publisher)
Created2011
Description
ABSTRACT To meet stringent market demands, manufacturers must produce Radio Frequency (RF) transceivers that provide wireless communication between electronic components used in consumer products at extremely low cost. Semiconductor manufacturers are in a steady race to increase integration levels through advanced system-on-chip (SoC) technology. The testing costs of these devices tend to increase with higher integration levels. As the integration levels increase and the devices get faster, the need for high-calibre low cost test equipment become highly dominant. However testing the overall system becomes harder and more expensive. Traditionally, the transceiver system is tested in two steps utilizing high-calibre RF instrumentation and mixed-signal testers, with separate measurement setups for transmitter and receiver paths. Impairments in the RF front-end, such as the I/Q gain and phase imbalance and nonlinearity, severely affect the performance of the device. The transceiver needs to be characterized in terms of these impairments in order to guarantee good performance and specification requirements. The motivation factor for this thesis is to come up with a low cost and computationally simple extraction technique of these impairments. In the proposed extraction technique, the mapping between transmitter input signals and receiver output signals are used to extract the impairment and nonlinearity parameters. This is done with the help of detailed mathematical modeling of the transceiver. While the overall behavior is nonlinear, both linear and nonlinear models to be used under different test setups are developed. A two step extraction technique has been proposed in this work. The extraction of system parameters is performed by using the mathematical model developed along with a genetic algorithm implemented in MATLAB. The technique yields good extraction results with reasonable error. It uses simple mathematical operation which makes the extraction fast and computationally simple when compared to other existing techniques such as traditional two step dedicated approach, Nonlinear Solver (NLS) approach, etc. It employs frequency domain analysis of low frequency input and output signals, over cumbersome time domain computations. Thus a test method, including detailed behavioral modeling of the transceiver, appropriate test signal design along with a simple algorithm for extraction is presented.
ContributorsSreenivassan, Aiswariya (Author) / Ozev, Sule (Thesis advisor) / Kiaei, Sayfe (Committee member) / Bakkaloglu, Bertan (Committee member) / Arizona State University (Publisher)
Created2011
Description
The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. The transition frequency of the device is demonstrated to be 45GHz, which makes the MESFET suitable for applications in high power RF power amplifier designs. Also, high breakdown voltage and low turn-on resistance make it the ideal choice for switches in the switching regulator designs. One of the anticipated applications of the MESFET is for the pass device for a low dropout linear regulator. Conventional NMOS and PMOS linear regulators suffer from high dropout voltage, low bandwidth and poor stability issues. In contrast, the N-MESFET pass transistor can provide an ultra-low dropout voltage and high bandwidth without the need for an external compensation capacitor to ensure stability. In this thesis, the design theory and problems of the conventional linear regulators are discussed. N-MESFET low dropout regulators are evaluated and characterized. The error amplifier used a folded cascode architecture with gain boosting. The source follower topology is utilized as the buffer to sink the gate leakage current from the MESFET. A shunt-feedback transistor is added to reduce the output impedance and provide the current adaptively. Measurement results show that the dropout voltage is less than 150 mV for a 1A load current at 1.8V output. Radiation measurements were done for discrete MESFET and fully integrated LDO regulators, which demonstrate their radiation tolerance ability for aerospace applications.
ContributorsChen, Bo (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2013
Description
The object of this study was a 26 year old residential Photovoltaic (PV) monocrystalline silicon (c-Si) power plant, called Solar One, built by developer John F. Long in Phoenix, Arizona (a hot-dry field condition). The task for Arizona State University Photovoltaic Reliability Laboratory (ASU-PRL) graduate students was to evaluate the power plant through visual inspection, electrical performance, and infrared thermography. The purpose of this evaluation was to measure and understand the extent of degradation to the system along with the identification of the failure modes in this hot-dry climatic condition. This 4000 module bipolar system was originally installed with a 200 kW DC output of PV array (17 degree fixed tilt) and an AC output of 175 kVA. The system was shown to degrade approximately at a rate of 2.3% per year with no apparent potential induced degradation (PID) effect. The power plant is made of two arrays, the north array and the south array. Due to a limited time frame to execute this large project, this work was performed by two masters students (Jonathan Belmont and Kolapo Olakonu) and the test results are presented in two masters theses. This thesis presents the results obtained on the north array and the other thesis presents the results obtained on the south array. The resulting study showed that PV module design, array configuration, vandalism, installation methods and Arizona environmental conditions have had an effect on this system's longevity and reliability. Ultimately, encapsulation browning, higher series resistance (potentially due to solder bond fatigue) and non-cell interconnect ribbon breakages outside the modules were determined to be the primary causes for the power loss.
ContributorsBelmont, Jonathan (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Henderson, Mark (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2013
Description
Potential induced degradation (PID) due to high system voltages is one of the major degradation mechanisms in photovoltaic (PV) modules, adversely affecting their performance due to the combined effects of the following factors: system voltage, superstrate/glass surface conductivity, encapsulant conductivity, silicon nitride anti-reflection coating property and interface property (glass/encapsulant; encapsulant/cell; encapsulant/backsheet). Previous studies carried out at ASU's Photovoltaic Reliability Laboratory (ASU-PRL) showed that only negative voltage bias (positive grounded systems) adversely affects the performance of commonly available crystalline silicon modules. In previous studies, the surface conductivity of the glass surface was obtained using either conductive carbon layer extending from the glass surface to the frame or humidity inside an environmental chamber. This thesis investigates the influence of glass surface conductivity disruption on PV modules. In this study, conductive carbon was applied only on the module's glass surface without extending to the frame and the surface conductivity was disrupted (no carbon layer) at 2cm distance from the periphery of frame inner edges. This study was carried out under dry heat at two different temperatures (60 °C and 85 °C) and three different negative bias voltages (-300V, -400V, and -600V). To replicate closeness to the field conditions, half of the selected modules were pre-stressed under damp heat for 1000 hours (DH 1000) and the remaining half under 200 hours of thermal cycling (TC 200). When the surface continuity was disrupted by maintaining a 2 cm gap from the frame to the edge of the conductive layer, as demonstrated in this study, the degradation was found to be absent or negligibly small even after 35 hours of negative bias at elevated temperatures. This preliminary study appears to indicate that the modules could become immune to PID losses if the continuity of the glass surface conductivity is disrupted at the inside boundary of the frame. The surface conductivity of the glass, due to water layer formation in a humid condition, close to the frame could be disrupted just by applying a water repelling (hydrophobic) but high transmittance surface coating (such as Teflon) or modifying the frame/glass edges with water repellent properties.
ContributorsTatapudi, Sai Ravi Vasista (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Srinivasan, Devarajan (Committee member) / Rogers, Bradley (Committee member) / Arizona State University (Publisher)
Created2012
Description
ABSTRACT Ongoing research into wireless transceivers in the 60 GHz band is required to address the demand for high data rate communications systems at a frequency where signal propagation is challenging even over short ranges. This thesis proposes a mixer architecture in Complementary Metal Oxide Semiconductor (CMOS) technology that uses a voltage controlled oscillator (VCO) operating at a fractional multiple of the desired output signal. The proposed topology is different from conventional subharmonic mixing in that the oscillator phase generation circuitry usually required for such a circuit is unnecessary. Analysis and simulations are performed on the proposed mixer circuit in an IBM 90 nm RF process on a 1.2 V supply. A typical RF transmitter system is considered in determining the block requirements needed for the mixer to meet the IEEE 802.11ad 60 GHz Draft Physical Layer Specification. The proposed circuit has a conversion loss of 21 dB at 60 GHz with a 5 dBm LO power at 20 GHz. Input-referred third-order intercept point (IIP3) is 2.93 dBm. The gain and linearity of the proposed mixer are sufficient for Orthogonal Frequency Division Multiplexing (OFDM) modulation at 60 GHz with a transmitted data rate of over 4 Gbps.
ContributorsMartino, Todd Jeffrey (Author) / Kiaei, Sayfe (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Aberle, James T., 1961- (Committee member) / Arizona State University (Publisher)
Created2010
Description
The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application.
ContributorsLepkowski, William (Author) / Thornton, Trevor (Thesis advisor) / Bakkaloglu, Bertan (Committee member) / Goryll, Michael (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2010
Description
Building applied photovoltaics (BAPV) is a major application sector for photovoltaics (PV). Due to the negative temperature coefficient of power output, the performance of a PV module decreases as the temperature of the module increases. In hot climatic conditions, such as the summer in Arizona, the operating temperature of a BAPV module can reach as high as 90°C. Considering a typical 0.5%/°C power drop for crystalline silicon (c-Si) modules, a performance decrease of approximately 30% would be expected during peak summer temperatures due to the difference between rated temperature (25°C) and operating temperature (~90°C) of the modules. Also, in a worst-case scenario, such as partial shading of the PV cells of air gap-free BAPV modules, some of the components could attain temperatures that would be high enough to compromise the safety and functionality requirements of the module and its components. Based on the temperature and weather data collected over a year in Arizona, a mathematical thermal model has been developed and presented in this paper to predict module temperature for five different air gaps (0", 1", 2", 3", and 4"). For comparison, modules with a thermally-insulated (R30) back were evaluated to determine the worst-case scenario. This thesis also provides key technical details related to the specially-built, simulated rooftop structure; the mounting configuration of the PV modules on the rooftop structure; the LabVIEW program that was developed for data acquisition and the MATLAB program for developing the thermal models. In order to address the safety issue, temperature test results (obtained in accordance with IEC 61730-2 and UL 1703 safety standards) are presented and analyzed for nine different components of a PV module, i.e., the front glass, substrate/backsheet (polymer), PV cell, j-box ambient, j-box surface, positive terminal, backsheet inside j-box, field wiring, and diode. The temperature test results obtained for about 140 crystalline silicon modules from a large number of manufacturers who tested modules between 2006 and 2009 at ASU/TÜV-PTL were analyzed and presented in this paper under three test conditions, i.e., short-circuit, open-circuit, and short-circuit and shaded. Also, the nominal operating cell temperatures (NOCTs) of the BAPV modules and insulated-back PV modules are presented in this paper for use by BAPV module designers and installers.
ContributorsOh, Jaewon (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley R (Committee member) / Macia, Narciso F. (Committee member) / Arizona State University (Publisher)
Created2010
Description
Solar photovoltaic (PV) generation has seen significant growth in 2021, with an increase of around 22% and exceeding 1000 TWh. However, this has also led to reliability and durability issues, particularly potential induced degradation (PID), which can reduce module output by up to 30%. This study uses cell- and module-level analysis to investigate the impact of superstrate, encapsulant, and substrate on PID.The influence of different substrates and encapsulants is studied using one-cell modules, showing that substrates with poor water-blocking properties can worsen PID, and encapsulants with lower volumetric resistance can conduct easily under damp conditions, enabling PID mechanisms (results show maximum degradation of 9%). Applying an anti-soiling coating on the front glass (superstrate) reduces PID by nearly 53%. Typical superstrates have sodium which accelerates the PID process, and therefore, using such coatings can lessen the PID problem.
At the module level, the study examines the influence of weakened interface adhesion strengths in traditional Glass-Backsheet (GB) and emerging Glass-Glass (GG) (primarily bifacial modules) constructions. The findings show nearly 64% more power degradation in GG modules than in GB. Moreover, the current methods for detecting PID use new modules, which can give inaccurate information instead of DH-stressed modules for PID testing, as done in this work.
A comprehensive PID susceptibility analysis for multiple fresh bifacial constructions shows significant degradation from 20 to 50% in various constructions. The presence of glass as the substrate exacerbates the PID problem due to more ionic activity available from the two glass sides. Recovery experiments are also conducted to understand the extent of the PID issue.
Overall, this study identifies, studies, and explains the impact of superstrate, substrate, and encapsulant on the underlying PID mechanisms. Various pre- and post-stress characterization tests, including light and dark current-voltage (I-V) tests, electroluminescence (EL) imaging, infrared (IR) imaging, and UV fluorescence (UVF) imaging, are used to evaluate the findings. This study is significant as it provides insights into the PID issues in solar PV systems, which can help improve their performance and reliability.
ContributorsMahmood, Farrukh ibne (Author) / Tamizhmani, Govindasamy (Thesis advisor) / Rogers, Bradley (Committee member) / Oh, Jaewon (Committee member) / Rajadas, John (Committee member) / Arizona State University (Publisher)
Created2023