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Description
ABSTRACT As referenced in Navajo ceremonial prayers and songs, "Saad bee hahoozhood jini," it began harmoniously with language. This dissertation examines and celebrates in new ways the meaning of language in Navajo literature. The first chapter is an introduction of this dissertation. I share my personal experiences with language, both English and Navajo, and how it has shaped me to be the person I am today as a Navajo speaker, student, educator, and professional. The second chapter contains an analysis and review of Western ideology of feminism and its place in Navajo society and a comparative study of several works written by Navajo authors, including Laura Tohe, Luci Tapahonso, and Nia Francisco, and how their creative works reflect the foundation of Navajo culture, Asdzaa Nadleehe, Changing Woman. The third chapter presents my own short fiction of Navajo characters living in today's society, a society that entails both positive and negative issues of Navajo life. These stories present realistic twenty-first century environments on the Navajo reservation. The fourth chapter consists of a short fiction written originally in the Navajo language. The story also represents the celebration of Navajo language as it thrives in today's time of tribal and cultural struggles. The sense of it being told in Navajo celebrates and preserves Navajo culture and language. The final chapter is the beginning of an oral narrative presented in written form, that of my grandmother's life story. This introduction of her story also is in itself a commemoration of language, oral Navajo language.
ContributorsWheeler, Jennifer L (Author) / Ortiz, Simon (Thesis advisor) / Tohe, Laura (Committee member) / Blasingame, James (Committee member) / Arizona State University (Publisher)
Created2011
Description
Lossy compression is a form of compression that slightly degrades a signal in ways that are ideally not detectable to the human ear. This is opposite to lossless compression, in which the sample is not degraded at all. While lossless compression may seem like the best option, lossy compression, which is used in most audio and video, reduces transmission time and results in much smaller file sizes. However, this compression can affect quality if it goes too far. The more compression there is on a waveform, the more degradation there is, and once a file is lossy compressed, this process is not reversible. This project will observe the degradation of an audio signal after the application of Singular Value Decomposition compression, a lossy compression that eliminates singular values from a signal’s matrix.
ContributorsHirte, Amanda (Author) / Kosut, Oliver (Thesis director) / Bliss, Daniel (Committee member) / Electrical Engineering Program (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
For my project, I delve into the relationships of Victor and the Monster as well as the relationships Victor shares with other characters that were underdeveloped within the original novel by Mary Shelley in the novel Franeknstein. I examine their relationships in two components. The first through my own interpretation of Victor and the Monster’s relationship within a creative writing piece that extends the novel as if Victor had lived rather than died in the arctic in order to explore the possibilities of a more complex set of relationships between Victor and the Monster than simply creator-creation. My writing focuses on the development of their relationship once all they have left is each other. The second part of my project focuses on an analytical component. I analyze and cite the reasoning for my creative take on Victor and the Monster as well as their relationship within the novel and Mary Shelley’s intentions.
ContributorsHodge Smith, Elizabeth Ann (Author) / Fette, Don (Thesis director) / Hoyt, Heather (Committee member) / Historical, Philosophical & Religious Studies (Contributor, Contributor) / Historical, Philosophical & Religious Studies, Sch (Contributor, Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
In this essay, I set out to explore and analyze how Shirley Jackson’s The Haunting of Hill House, and the character of Eleanor Vance in particular, disrupts and redefines the traditional conventions of the Female Gothic within the context of the 20th century. I utilize Tania Modleski's gendering of Freud's theory of psychoanalysis in her exploration of the ‘Female Uncanny,’ arguing that the source of the Uncanny in the Female Gothic can be found in the "fear of being lost in the mother." I argue that Jackson's complex personal life, including her fraught relationship with her mother and her difficult marriage with literary critic Edgar Hyman, color her fiction and the primary motivations of her protagonist, Eleanor Vance. I also outline the traditional structure of the Gothic novel and the heroine's journey. With the necessary context provided, I then explain how Eleanor Vance’s character rejects these Gothic traditions and ushers in a new era of Female Gothic fiction.
ContributorsAlcantar, Sarah (Author) / Fette, Donald (Thesis director) / Zarka, Emily (Committee member) / Department of Management and Entrepreneurship (Contributor) / Department of English (Contributor) / Barrett, The Honors College (Contributor)
Created2021-05
Description
Following the success in incorporating perceptual models in audio coding algorithms, their application in other speech/audio processing systems is expanding. In general, all perceptual speech/audio processing algorithms involve minimization of an objective function that directly/indirectly incorporates properties of human perception. This dissertation primarily investigates the problems associated with directly embedding an auditory model in the objective function formulation and proposes possible solutions to overcome high complexity issues for use in real-time speech/audio algorithms. Specific problems addressed in this dissertation include: 1) the development of approximate but computationally efficient auditory model implementations that are consistent with the principles of psychoacoustics, 2) the development of a mapping scheme that allows synthesizing a time/frequency domain representation from its equivalent auditory model output. The first problem is aimed at addressing the high computational complexity involved in solving perceptual objective functions that require repeated application of auditory model for evaluation of different candidate solutions. In this dissertation, a frequency pruning and a detector pruning algorithm is developed that efficiently implements the various auditory model stages. The performance of the pruned model is compared to that of the original auditory model for different types of test signals in the SQAM database. Experimental results indicate only a 4-7% relative error in loudness while attaining up to 80-90 % reduction in computational complexity. Similarly, a hybrid algorithm is developed specifically for use with sinusoidal signals and employs the proposed auditory pattern combining technique together with a look-up table to store representative auditory patterns. The second problem obtains an estimate of the auditory representation that minimizes a perceptual objective function and transforms the auditory pattern back to its equivalent time/frequency representation. This avoids the repeated application of auditory model stages to test different candidate time/frequency vectors in minimizing perceptual objective functions. In this dissertation, a constrained mapping scheme is developed by linearizing certain auditory model stages that ensures obtaining a time/frequency mapping corresponding to the estimated auditory representation. This paradigm was successfully incorporated in a perceptual speech enhancement algorithm and a sinusoidal component selection task.
ContributorsKrishnamoorthi, Harish (Author) / Spanias, Andreas (Thesis advisor) / Papandreou-Suppappola, Antonia (Committee member) / Tepedelenlioğlu, Cihan (Committee member) / Tsakalis, Konstantinos (Committee member) / Arizona State University (Publisher)
Created2011
Description
Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current Shunt Monitor (CSM) systems have various applications for precise current monitoring of those aforementioned applications. CSMs enable current measurement across an external sense resistor (RS) in series to current flow. Two different types of CSMs designed and characterized in this paper. First design used direct current reading method and the other design used indirect current reading method. Proposed CSM systems can sense power supply current ranging from 1mA to 200mA for the direct current reading topology and from 1mA to 500mA for the indirect current reading topology across a typical board Cu-trace resistance of 1 ohm with less than 10 µV input-referred offset, 0.3 µV/°C offset drift and 0.1% accuracy for both topologies. Proposed systems avoid using a costly zero-temperature coefficient (TC) sense resistor that is normally used in typical CSM systems. Instead, both of the designs used existing Cu-trace on the printed circuit board (PCB) in place of the costly resistor. The systems use chopper stabilization at the front-end amplifier signal path to suppress input-referred offset down to less than 10 µV. Switching current-mode (SI) FIR filtering technique is used at the instrumentation amplifier output to filter out the chopping ripple caused by input offset and flicker noise by averaging half of the phase 1 signal and the other half of the phase 2 signal. In addition, residual offset mainly caused by clock feed-through and charge injection of the chopper switches at the chopping frequency and its multiple frequencies notched out by the since response of the SI-FIR filter. A frequency domain Sigma Delta ADC which is used for the indirect current reading type design enables a digital interface to processor applications with minimally added circuitries to build a simple 1st order Sigma Delta ADC. The CSMs are fabricated on a 0.7µm CMOS process with 3 levels of metal, with maximum Vds tolerance of 8V and operates across a common mode range of 0 to 26V for the direct current reading type and of 0 to 30V for the indirect current reading type achieving less than 10nV/sqrtHz of flicker noise at 100 Hz for both approaches. By using a semi-digital SI-FIR filter, residual chopper offset is suppressed down to 0.5mVpp from a baseline of 8mVpp, which is equivalent to 25dB suppression.
ContributorsYeom, Hyunsoo (Author) / Bakkaloglu, Bertan (Thesis advisor) / Kiaei, Sayfe (Committee member) / Ozev, Sule (Committee member) / Yu, Hongyu (Committee member) / Arizona State University (Publisher)
Created2011
Description
Recent changes in the energy markets structure combined with the conti-nuous load growth have caused power systems to be operated under more stressed conditions. In addition, the nature of power systems has also grown more complex and dynamic because of the increasing use of long inter-area tie-lines and the high motor loads especially those comprised mainly of residential single phase A/C motors. Therefore, delayed voltage recovery, fast voltage collapse and short term voltage stability issues in general have obtained significant importance in relia-bility studies. Shunt VAr injection has been used as a countermeasure for voltage instability. However, the dynamic and fast nature of short term voltage instability requires fast and sufficient VAr injection, and therefore dynamic VAr devices such as Static VAr Compensators (SVCs) and STATic COMpensators (STAT-COMs) are used. The location and size of such devices are optimized in order to improve their efficiency and reduce initial costs. In this work time domain dy-namic analysis was used to evaluate trajectory voltage sensitivities for each time step. Linear programming was then performed to determine the optimal amount of required VAr injection at each bus, using voltage sensitivities as weighting factors. Optimal VAr injection values from different operating conditions were weighted and averaged in order to obtain a final setting of the VAr requirement. Some buses under consideration were either assigned very small VAr injection values, or not assigned any value at all. Therefore, the approach used in this work was found to be useful in not only determining the optimal size of SVCs, but also their location.
ContributorsSalloum, Ahmed (Author) / Vittal, Vijay (Thesis advisor) / Heydt, Gerald (Committee member) / Ayyanar, Raja (Committee member) / Arizona State University (Publisher)
Created2011
Description
This research work describes the design of a fault current limiter (FCL) using digital logic and a microcontroller based data acquisition system for an ultra fast pilot protection system. These systems have been designed according to the requirements of the Future Renewable Electric Energy Delivery and Management (FREEDM) system (or loop), a 1 MW green energy hub. The FREEDM loop merges advanced power electronics technology with information tech-nology to form an efficient power grid that can be integrated with the existing power system. With the addition of loads to the FREEDM system, the level of fault current rises because of increased energy flow to supply the loads, and this requires the design of a limiter which can limit this current to a level which the existing switchgear can interrupt. The FCL limits the fault current to around three times the rated current. Fast switching Insulated-gate bipolar transistor (IGBT) with its gate control logic implements a switching strategy which enables this operation. A complete simulation of the system was built on Simulink and it was verified that the FCL limits the fault current to 1000 A compared to more than 3000 A fault current in the non-existence of a FCL. This setting is made user-defined. In FREEDM system, there is a need to interrupt a fault faster or make intelligent deci-sions relating to fault events, to ensure maximum availability of power to the loads connected to the system. This necessitates fast acquisition of data which is performed by the designed data acquisition system. The microcontroller acquires the data from a current transformer (CT). Mea-surements are made at different points in the FREEDM system and merged together, to input it to the intelligent protection algorithm that has been developed by another student on the project. The algorithm will generate a tripping signal in the event of a fault. The developed hardware and the programmed software to accomplish data acquisition and transmission are presented here. The designed FCL ensures that the existing switchgear equipments need not be replaced thus aiding future power system expansion. The developed data acquisition system enables fast fault sensing in protection schemes improving its reliability.
ContributorsThirumalai, Arvind (Author) / Karady, George G. (Thesis advisor) / Vittal, Vijay (Committee member) / Hedman, Kory (Committee member) / Arizona State University (Publisher)
Created2011
Description
There will always be a need for high current/voltage transistors. A transistor that has the ability to be both or either of these things is the silicon metal-silicon field effect transistor (MESFET). An additional perk that silicon MESFET transistors have is the ability to be integrated into the standard silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) process flow. This makes a silicon MESFET transistor a very valuable device for use in any standard CMOS circuit that may usually need a separate integrated circuit (IC) in order to switch power on or from a high current/voltage because it allows this function to be performed with a single chip thereby cutting costs. The ability for the MESFET to cost effectively satisfy the needs of this any many other high current/voltage device application markets is what drives the study of MESFET optimization. Silicon MESFETs that are integrated into standard SOI CMOS processes often receive dopings during fabrication that would not ideally be there in a process made exclusively for MESFETs. Since these remnants of SOI CMOS processing effect the operation of a MESFET device, their effect can be seen in the current-voltage characteristics of a measured MESFET device. Device simulations are done and compared to measured silicon MESFET data in order to deduce the cause and effect of many of these SOI CMOS remnants. MESFET devices can be made in both fully depleted (FD) and partially depleted (PD) SOI CMOS technologies. Device simulations are used to do a comparison of FD and PD MESFETs in order to show the advantages and disadvantages of MESFETs fabricated in different technologies. It is shown that PD MESFET have the highest current per area capability. Since the PD MESFET is shown to have the highest current capability, a layout optimization method to further increase the current per area capability of the PD silicon MESFET is presented, derived, and proven to a first order.
ContributorsSochacki, John (Author) / Thornton, Trevor J (Thesis advisor) / Schroder, Dieter (Committee member) / Vasileska, Dragica (Committee member) / Goryll, Michael (Committee member) / Arizona State University (Publisher)
Created2011
Description
The increased use of commercial complementary metal-oxide-semiconductor (CMOS) technologies in harsh radiation environments has resulted in a new approach to radiation effects mitigation. This approach utilizes simulation to support the design of integrated circuits (ICs) to meet targeted tolerance specifications. Modeling the deleterious impact of ionizing radiation on ICs fabricated in advanced CMOS technologies requires understanding and analyzing the basic mechanisms that result in buildup of radiation-induced defects in specific sensitive regions. Extensive experimental studies have demonstrated that the sensitive regions are shallow trench isolation (STI) oxides. Nevertheless, very little work has been done to model the physical mechanisms that result in the buildup of radiation-induced defects and the radiation response of devices fabricated in these technologies. A comprehensive study of the physical mechanisms contributing to the buildup of radiation-induced oxide trapped charges and the generation of interface traps in advanced CMOS devices is presented in this dissertation. The basic mechanisms contributing to the buildup of radiation-induced defects are explored using a physical model that utilizes kinetic equations that captures total ionizing dose (TID) and dose rate effects in silicon dioxide (SiO2). These mechanisms are formulated into analytical models that calculate oxide trapped charge density (Not) and interface trap density (Nit) in sensitive regions of deep-submicron devices. Experiments performed on field-oxide-field-effect-transistors (FOXFETs) and metal-oxide-semiconductor (MOS) capacitors permit investigating TID effects and provide a comparison for the radiation response of advanced CMOS devices. When used in conjunction with closed-form expressions for surface potential, the analytical models enable an accurate description of radiation-induced degradation of transistor electrical characteristics. In this dissertation, the incorporation of TID effects in advanced CMOS devices into surface potential based compact models is also presented. The incorporation of TID effects into surface potential based compact models is accomplished through modifications of the corresponding surface potential equations (SPE), allowing the inclusion of radiation-induced defects (i.e., Not and Nit) into the calculations of surface potential. Verification of the compact modeling approach is achieved via comparison with experimental data obtained from FOXFETs fabricated in a 90 nm low-standby power commercial bulk CMOS technology and numerical simulations of fully-depleted (FD) silicon-on-insulator (SOI) n-channel transistors.
ContributorsSanchez Esqueda, Ivan (Author) / Barnaby, Hugh J (Committee member) / Schroder, Dieter (Thesis advisor) / Schroder, Dieter K. (Committee member) / Holbert, Keith E. (Committee member) / Gildenblat, Gennady (Committee member) / Arizona State University (Publisher)
Created2011