Matching Items (4)
Description
The performance of kilometer-scale electron accelerators, which are used for high energy physics and next-generation light sources as well as meter-scale ultra-fast electron diffraction setups is limited by the brightness of electron sources. A potential emerging candidate for such applications is the family of alkali and bi-alkali antimonides. Much of the physics of photoemission from such semiconductor photocathodes is not fully understood even today, which poses a hindrance to the complete exploration and optimization of their photoemission properties. This thesis presents the theoretical and experimental measurements which lead to advances in the understanding of the photoemission process and properties of cesium-antimonide photocathodes. First, the growth of high quantum efficiency (QE), atomically smooth and chemically homogeneous Cs$_3$Sb cathodes on lattice-matched strontium titanate substrates (STO) is demonstrated. The roughness-induced mean transverse energies (MTE) simulations indicate that the contribution to MTE from nanoscale surface roughness of Cs$_3$Sb cathodes grown on STO is inconsequential over typically used field gradients in photoinjectors. Second, the formulation of a new approach to model photoemission from cathodes with disordered surfaces is demonstrated. The model is used to explain near-threshold photoemission from thin film Cs$_3$Sb cathodes. This model suggests that the MTE values may get limited to higher values due to the defect density of states near the valence band maximum. Third, the detailed measurements of MTE and kinetic energy distribution spectra along with QE from Cs$_3$Sb cathodes using the photoemission electron microscope are presented. These measurements indicate that Cs$_3$Sb cathodes have a work function in the range of 1.5-1.6 eV. When photoemitting near this work function energy, the MTE nearly converges to the thermal limit of 26 meV. However, the QE is extremely low, of the order of 10$^{-7}$, which limits the operation of these photocathodes for high current applications. Lastly, the growth of Cs$_3$Sb cathodes using the ion beam assisted molecular beam deposition (IBA-MBE) technique is demonstrated. This technique has the potential to grow epitaxial Cs$_3$Sb cathodes in a more reproducible, easier fashion. Structural characterization of such cathodes via tools such as reflection high energy electron diffraction (RHEED) and x-ray diffraction (XRD) will be necessary to investigate the role of the IBA-MBE technique in facilitating the epitaxial, ordered growth of alkali-antimonides.
ContributorsSaha, Pallavi (Author) / Karkare, Siddharth (Thesis advisor) / Bennett, Peter (Committee member) / Nemanich, Robert (Committee member) / Kaindl, Robert (Committee member) / Arizona State University (Publisher)
Created2023
Description
The performance of accelerator applications like X-ray free electron lasers (XFELs)and ultrafast electron diffraction (UED) and microscopy (UEM) experiments is limited
by the brightness of electron beams generated by photoinjectors. In order to
maximize the brightness of an electron beam it is essential that electrons are emitted
from photocathodes with the smallest possible mean transverse energy (MTE).
Metallic photocathodes hold the record for the smallest MTE ever measured at 5
meV from a Cu(100) single crystal photocathode operated near the photoemission
threshold and cooled to 30 K. However such photocathodes have two major limitations:
poor surface stability, and a low quantum efficiency (QE) which leads to
MTE degrading non-linear photoemission effects when extracting large charge densities.
This thesis investigates the efficacy of using a graphene protective layer in order
to improve the stability of a Cu(110) single crystalline surface. The contribution to
MTE from non-linear photoemission effects is measured from a Cu(110) single crystal
photocathode at a variety of excess energies, laser fluences, and laser pulse lengths.
To conclude this thesis, the design and research capabilities of the Photocathode and
Bright Beams Lab (PBBL) are presented. Such a lab is required to develop cathode
technology to mitigate the practical limitations of metallic photocathodes.
ContributorsKnill, Christopher John (Author) / Karkare, Siddharth (Thesis advisor) / Drucker, Jeffery (Committee member) / Kaindl, Robert (Committee member) / Teitelbaum, Samuel (Committee member) / Arizona State University (Publisher)
Created2023
Description
Hardware implementation of deep neural networks is earning significant importance nowadays. Deep neural networks are mathematical models that use learning algorithms inspired by the brain. Numerous deep learning algorithms such as multi-layer perceptrons (MLP) have demonstrated human-level recognition accuracy in image and speech classification tasks. Multiple layers of processing elements called neurons with several connections between them called synapses are used to build these networks. Hence, it involves operations that exhibit a high level of parallelism making it computationally and memory intensive. Constrained by computing resources and memory, most of the applications require a neural network which utilizes less energy. Energy efficient implementation of these computationally intense algorithms on neuromorphic hardware demands a lot of architectural optimizations. One of these optimizations would be the reduction in the network size using compression and several studies investigated compression by introducing element-wise or row-/column-/block-wise sparsity via pruning and regularization. Additionally, numerous recent works have concentrated on reducing the precision of activations and weights with some reducing to a single bit. However, combining various sparsity structures with binarized or very-low-precision (2-3 bit) neural networks have not been comprehensively explored. Output activations in these deep neural network algorithms are habitually non-binary making it difficult to exploit sparsity. On the other hand, biologically realistic models like spiking neural networks (SNN) closely mimic the operations in biological nervous systems and explore new avenues for brain-like cognitive computing. These networks deal with binary spikes, and they can exploit the input-dependent sparsity or redundancy to dynamically scale the amount of computation in turn leading to energy-efficient hardware implementation. This work discusses configurable spiking neuromorphic architecture that supports multiple hidden layers exploiting hardware reuse. It also presents design techniques for minimum-area/-energy DNN hardware with minimal degradation in accuracy. Area, performance and energy results of these DNN and SNN hardware is reported for the MNIST dataset. The Neuromorphic hardware designed for SNN algorithm in 28nm CMOS demonstrates high classification accuracy (>98% on MNIST) and low energy (51.4 - 773 (nJ) per classification). The optimized DNN hardware designed in 40nm CMOS that combines 8X structured compression and 3-bit weight precision showed 98.4% accuracy at 33 (nJ) per classification.
ContributorsKolala Venkataramanaiah, Shreyas (Author) / Seo, Jae-Sun (Thesis advisor) / Chakrabarti, Chaitali (Committee member) / Cao, Yu (Committee member) / Arizona State University (Publisher)
Created2018
Description
Coarse-grained Reconfigurable Arrays (CGRAs) are promising accelerators capable
of accelerating even non-parallel loops and loops with low trip-counts. One challenge
in compiling for CGRAs is to manage both recurring and nonrecurring variables in
the register file (RF) of the CGRA. Although prior works have managed recurring
variables via rotating RF, they access the nonrecurring variables through either a
global RF or from a constant memory. The former does not scale well, and the latter
degrades the mapping quality. This work proposes a hardware-software codesign
approach in order to manage all the variables in a local nonrotating RF. Hardware
provides modulo addition based indexing mechanism to enable correct addressing
of recurring variables in a nonrotating RF. The compiler determines the number of
registers required for each recurring variable and configures the boundary between the
registers used for recurring and nonrecurring variables. The compiler also pre-loads
the read-only variables and constants into the local registers in the prologue of the
schedule. Synthesis and place-and-route results of the previous and the proposed RF
design show that proposed solution achieves 17% better cycle time. Experiments of
mapping several important and performance-critical loops collected from MiBench
show proposed approach improves performance (through better mapping) by 18%,
compared to using constant memory.
of accelerating even non-parallel loops and loops with low trip-counts. One challenge
in compiling for CGRAs is to manage both recurring and nonrecurring variables in
the register file (RF) of the CGRA. Although prior works have managed recurring
variables via rotating RF, they access the nonrecurring variables through either a
global RF or from a constant memory. The former does not scale well, and the latter
degrades the mapping quality. This work proposes a hardware-software codesign
approach in order to manage all the variables in a local nonrotating RF. Hardware
provides modulo addition based indexing mechanism to enable correct addressing
of recurring variables in a nonrotating RF. The compiler determines the number of
registers required for each recurring variable and configures the boundary between the
registers used for recurring and nonrecurring variables. The compiler also pre-loads
the read-only variables and constants into the local registers in the prologue of the
schedule. Synthesis and place-and-route results of the previous and the proposed RF
design show that proposed solution achieves 17% better cycle time. Experiments of
mapping several important and performance-critical loops collected from MiBench
show proposed approach improves performance (through better mapping) by 18%,
compared to using constant memory.
ContributorsDave, Shail (Author) / Shrivastava, Aviral (Thesis advisor) / Ren, Fengbo (Committee member) / Ogras, Umit Y. (Committee member) / Arizona State University (Publisher)
Created2016