Development of Radiation Hardened High Voltage Super-Junction Power MOSFET
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Description
In recent years, the Silicon Super-Junction (SJ) power metal-oxide semiconductor field-effect transistor (MOSFET), has garnered significant interest from spacecraft designers. This is due to their high breakdown voltage and low specific on-state resistance characteristics. Most of the previous research work on power MOSFETS for space applications concentrated on improving the radiation tolerance of low to medium voltage (~ 300V) power MOSFETs. Therefore, understanding and improving the reliability of high voltage SJMOS for the harsh space radiation environment is an important endeavor.In this work, a 600V commercially available silicon planar gate SJMOS is used to study the SJ technology’s tolerance against total ionizing dose (TID) and destructive single event effects (SEE), such as, single event burnout (SEB) and single event gate rupture (SEGR). A technology computer aided design (TCAD) software tool is used to design the SJMOS and simulate its electrical characteristics.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.
Electrical characterization of SJMOS devices showed substantial decrease in threshold voltage and increase in leakage current due to TID. Therefore, as a solution to improve the TID tolerance, metal-nitride-oxide-semiconductor (MNOS) capacitors with different oxide
itride thickness combinations were fabricated and irradiated using a Co-60 gamma-source. Electrical characterization showed all samples with oxide
itride stack gate insulators exhibited significantly higher tolerance to irradiation when compared to metal-oxide-semiconductor capacitors.
Heavy ion testing of the SJMOS showed the device failed due to SEB and SEGR at 10% of maximum rated bias values. In this work, a 600V SJMOS structure is designed that is tolerant to both SEB and SEGR. In a SJMOS with planar gate, reducing the neck width improves the tolerance to SEGR but significantly changes the device electrical characteristics. The trench gate SJ device design is shown to overcome this problem. A buffer layer and larger P+-plug are added to the trench gate SJ power transistor to improve SEB tolerance. Using TCAD simulations, the proposed trench gate structure and the tested planar gate SJMOS are compared. The simulation results showed that the SEB and SEGR hardness in the proposed structure has improved by a factor of 10 and passes at the device’s maximum rated bias value with improved electrical performance.