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This thesis describes the design of a Single Event Transient (SET) duration measurement test-structure on the Global Foundries (previously IBM) 32-nm silicon-on insulator (SOI) process. The test structure is designed

This thesis describes the design of a Single Event Transient (SET) duration measurement test-structure on the Global Foundries (previously IBM) 32-nm silicon-on insulator (SOI) process. The test structure is designed for portability and allows quick design and implementation on a new process node. Such a test structure is critical in analyzing the effects of radiation on complementary metal oxide semi-conductor (CMOS) circuits.

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    Date Created
    • 2017
    Resource Type
  • Text
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    Note
    • Partial requirement for: M.S., Arizona State University, 2017
      Note type
      thesis
    • Includes bibliographical references (pages 57-60)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Lovish Masand

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