Description

Over decades, scientists have been scaling devices to increasingly smaller feature sizes for ever better performance of complementary metal-oxide semiconductor (CMOS) technology to meet requirements on speed, complexity, circuit density,

Over decades, scientists have been scaling devices to increasingly smaller feature sizes for ever better performance of complementary metal-oxide semiconductor (CMOS) technology to meet requirements on speed, complexity, circuit density, power consumption and ultimately cost required by many advanced applications. However, going to these ultra-scaled CMOS devices also brings some drawbacks. Aging due to bias-temperature-instability (BTI) and Hot carrier injection (HCI) is the dominant cause of functional failure in large scale logic circuits.

Reuse Permissions
  • 1.08 MB application/pdf

    Download count: 0

    Details

    Contributors
    Date Created
    • 2016
    Resource Type
  • Text
  • Collections this item is in
    Note
    • Partial requirement for: M.S.Tech, Arizona State University, 2016
      Note type
      thesis
    • Includes bibliographical references (page 35)
      Note type
      bibliography
    • Field of study: Electrical engineering

    Citation and reuse

    Statement of Responsibility

    by Ankita Bansal

    Machine-readable links