An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness and power consumption required by design. This was designed on 90nm low-standby power (LSP) process and utilized commercial CAD tools for testing.
Download count: 0
- Partial requirement for: M.S., Arizona State University, 2015Note typethesis
- Includes bibliographical references (pages 62-64)Note typebibliography
- Field of study: Electrical engineering