Full metadata
Title
Flash sharing in a time-interleaved pipeline ADC
Description
With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage. This work presents a design of 'sub-ADC shared in a time-interleaved pipeline ADC' in the IBM 8HP process. It has been implemented with an offset-compensated, kickback-compensated, fast decision making (large input bandwidth) and low power comparator that forms the core part of the design.
Date Created
2013
Contributors
- Bikkina, Phaneendra Kumar (Author)
- Barnaby, Hugh (Thesis advisor)
- Mikkola, Esko (Committee member)
- Kitchen, Jennifer (Committee member)
- Arizona State University (Publisher)
Resource Type
Extent
viii, 44 p. : ill. (some col.)
Language
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.18784
Statement of Responsibility
by Phaneendra Kumar Bikkina
Description Source
Viewed on Feb. 11, 2014
Level of coding
full
Note
Partial requirement for: M.S., Arizona State University, 2013
Note type
thesis
Includes bibliographical references (p. 42-44)
Note type
bibliography
Field of study: Electrical engineering
System Created
- 2013-10-08 04:24:45
System Modified
- 2021-08-30 01:38:08
- 2 years 8 months ago
Additional Formats