With the advent of parallel processing, primarily the time-interleaved pipeline ADCs, high speed and high resolution ADCs became a possibility. When these speeds touch giga samples per second and resolutions go beyond 12-bits, the parallelization becomes more extensive leading to repeated presence of several identical blocks in the architecture. This thesis discusses one such block, the sub-ADC (Flash ADC), of the pipeline and sharing it with more than two of the parallel processing channels thereby reducing area and power and input load capacitance to each stage.
Download count: 0
- Partial requirement for: M.S., Arizona State University, 2013Note typethesis
- Includes bibliographical references (p. 42-44)Note typebibliography
- Field of study: Electrical engineering