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With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to aggressive architectural changes for on-chi

With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to aggressive architectural changes for on-chip power management and rapid development to energy efficient hardware accelerators. Accordingly, the objective of this research work is to facilitate software developers to leverage these hardware techniques and improve energy efficiency of the system.

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    Date Created
    • 2013
    Resource Type
  • Text
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    Note
    • Partial requirement for: M.S., Arizona State University, 2013
      Note type
      thesis
    • Includes bibliographical references (p. 59-62)
      Note type
      bibliography
    • Field of study: Electrical engineering

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    by Digant Pareshkumar Desai

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